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KS152JB Universal Communications Controller
Technical Specifications
1.0 INTRODUCTION
The 80C152 Universal Communications Controller is an 8-bit microcontroller designed for the
intelligent management of peripheral systems or components. The 80C152 is a derivative of the
80C51 and retains the same functionality. These enhancements include: a high speed multi-proto-
col serial communication interface, two channels for DMA transfers, HOLD/HLDA bus control, a
fifth I/O port, expanded data memory, an
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KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 2 of 120 Ver. 0.9 KS152JB2 P4.0 - P4.7 P0.0 - P0.7 P2.0 - P2.7 PORT 4 PORT 0 PORT 2 DCON0 DCON1 DRIVERS DRIVERS DIRVERS SARL0 SARL1 SARH0 SARH1 DMA CONTROL DARL0 DARL1 DARH0 DARH1 RAM RAM PORT 4 PORT 0 PORT 2 BCRL0 ADDRESS 256 X 8 LATCH LATCH LATCH BCRL1 REGISTER BCRH0 BCRH1 ROM TCON PCON STACK ACC 8K X 8 B POINTER REGISTER TMOD
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KS152JB Universal Communications Controller Technical Specifications 2.1 Pin Description Table 1: PIN DESCRIPTION Name Description Port 0 Port 0 is an 8-bit open drain bi-directional I/O Port. As an output port each pin can sink 8 LS TTL inputs. Port 0 pins that have 1s written to them float, and in that state can be used as high-impedance inputs. external program memory if EBEN is pulled low. During accesses to external Data Memory, Port 0 always emits the low-order address byte and serves as th
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KS152JB Universal Communications Controller Technical Specifications Table 1: PIN DESCRIPTION Port 3 Port 3 is an 8-bit bi-directional I/O port with internal pullups. Port 3 pins that have 1s written to them are pulled high by the internal pullups, and in that state can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (I on the data sheet) because of the pullups. Port 3 also serves the IL, functions of various special features of the MCS-51 Famil
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KS152JB Universal Communications Controller Technical Specifications Table 1: PIN DESCRIPTION ALE Address Latch Enable output signal for latching the low byte of the address during accesses to external memory. In normal operation ALE is emitted at a constant rate of 1/6 the oscillator fre- quency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory. While in Reset, ALE remains at a constant high level.
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KS152JB Universal Communications Controller Technical Specifications 2.2 Special function Registers The following table lists the SFR’s present in 80152. Note that not all the addresses are occupied by SFR’s. The unoccupied addresses are not implemented and should not be used by the cus- tomer. Read access from these unoccupied locations will return unpredictable data, while write accesses will have no effect on the chip Table 2: SFR map for the cpu F8 IPN1 FF F0 B BCRL1 BCRH1 RFIFO MYSLOT F7 E8
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KS152JB Universal Communications Controller Technical Specifications between the RST pin being pulled low and the internal reset being generated. During this time the CPU continues its normal operations. The internal reset signal clears the SFRs except the port SFRs which have FFh written into them and the Stack Pointer which has 07h written to it. The SBUF is however in an indeterminate state. The Program Counter is reset to 0000h. The internal RAM is not affected by the reset and their content
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KS152JB Universal Communications Controller Technical Specifications Table 3: Reset Values of the SFRs SFR Name Reset Value SFR Name Reset Value IP XXX00000B SCON 00H IE 0XX00000B SBUF INDETERMINATE TMOD 00H PCON 0XXX0000B TCON 00H DARL0-1 INDETERMINATE DCON0-1 00H DARh0-1 INDETERMINATE GMOD X0000000B IFS 00H IEN1 XX000000B MYSLOT 00H IPN1 XX000000B PRBS 00H TCDCNT INDETERMINATE TCON 00H TFIFO INDETERMINATE TSTAT XX000100B 2.4 PORT STRUCTURES AND OPERATION The ports are all bidirectional. Each p
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KS152JB Universal Communications Controller Technical Specifications ADDRESS ADDR/DATA IDNAHI IDNAMX VCC VCC Internal Pullup P2.X P0.X Pin Pin 1 1 Q MUX Q MUX 0 PORT2OP 0 PORT0OP PORT2IP PORT0IP 3. Port 2 I/O Pad 1. Port 0 I/O Pad Alternate Output VCC Function VCC Weak Internal Weak Internal Pullup Pullup P1.X Pin P3.X Pin PORT1OP PORT3OP Alternate Output Function PORT1IP PORT3IP 2. Port 1 I/O Pad 4. Port 3,4,5 &6 I/O Pad Port bit I/O Pads As shown in Figure above, Ports 0 and 2 can emit either
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KS152JB Universal Communications Controller Technical Specifications Writing to a Port During the execution of an instruction that changes the value of a port SFR, the new value arrives at the port latch during S6P2. However, the port latch contents do not appear on the port pins till the next P1 phase. Therefore the new port data will appear on the port pins at S1P1 of the next machine cycle. Read-Modify-Write Feature Each port is split into its SFR and its corresponding I/O pad. Therefore ther
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KS152JB Universal Communications Controller Technical Specifications Table 4: EBEN EA Program PSEN EPSEN Comments Fetch via 0 0 P0, P2 Active Inactive Addresses 0 - 0FFFFH 0 1 N/A N/A N/A Invalid Combination 1 0 P5, P6 Inactive Addresses 0 - 0FFFFH 1 1 P5, P6 Inactive Active Addresses 0 - 1FFFH P0, P2 Active Inactive Addresses 0 - 2000H 2.6 ACCESSING EXTERNAL MEMORY External Memory is accessed if either of the following two c
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KS152JB Universal Communications Controller Technical Specifications During External Memory Accesses, both Ports 0 and 2 are used for Address/ Data transfer and therefore cannot be used for general I/O purposes. During external program fetches, Port 2 uses strong pullups to emit 1s. 2.7 TIMER/COUNTERS This has two 16-bit Timer/Counters, TM0 andTM1. Each of these Timer/Counters has two 8 bit registers which form the 16 bit counting register. For Timer/Counter TM0 they are TH0, the upper 8 bits re
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KS152JB Universal Communications Controller Technical Specifications 7654321 0 TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 TF1 Timer 1 overflow flag. Set by hardware on Timer/Counter overflow. Cleared by hardware when processor vectors to timer 1 interrupt routine. TR1 Timer 1 Run control bit. Set/Cleared by software to turn Timer/Counter on/off. TF0 Timer 0 overflow flag. Set by hardware on Timer/Counter overflow. Cleared by hardware when processor vectors to timer 0 interrupt routine. TR0 Timer 0 Run control bi
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KS152JB Universal Communications Controller Technical Specifications OSC S3P1 C/T I0 TLX THx Q INTERRUPT TFx 5 bits 8 bits Tx pin I1 TRx GATE INTx pin Timer/Counter in Mode 0 MODE 1 Mode 1 is similar to Mode 0 except that the counting register form a 16 bit counter, rather than a 13 bit counter. This means that all the bits of THx and TLx are used. . OSC S3P1 C/T I0 TLX INTERRUPT Q TFx 8 bits Tx pin I1 TRx Reload GATE INTx THx pin 8 bits Timer/Counter in Mode 2 MODE 2 In Mode 2, the timer/counte
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KS152JB Universal Communications Controller Technical Specifications Mode 3 is used in cases where an extra 8 bit timer is needed. With Timer 0 in Mode 3, Timer 1 can be turned on and off by switching it out of and into its own Mode 3. It can also be used as a baud rate generator for the serial port. C/T OSC S3P1 I0 TL0 Q INTERRUPT TF0 5 bits T0 pin I1 TR0 GATE INT0 pin S3P1 TH0 INTERRUPT TR1 TF1 8 bits Timer/Counter 0 in Mode 3 2.8 Interrupts The cpu has a provision for 11 different interrupt s
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KS152JB Universal Communications Controller Technical Specifications case of level triggered interrupt, the IE0 and IE1 flags are not cleared and will have to be cleared by the software. This is because in the level activated mode, it is the external requesting source that controls the interrupt flag bit rather than the on-chip hardware. The Timer 0 and 1 Interrupts are generated by the TF0 and TF1 flags. These flags are set by the overflow in the Timer 0 and Timer 1. The TF0 and TF1 flags are automat
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KS152JB Universal Communications Controller Technical Specifications 7 6 5 4 3 2 1 0 EGSTE EDMA1 EGSTV EDMA0 EGSRE EGSRV IEN1 (Additional interrupt enable register) (0C8H) Interrupt enable register for DMA and GSC interrupts. A 1 in any bit position enables that interrupt. IEN1.0 (EGSRV) - Enables the GSC valid receive interrupt. IEN1.1 (EGSRE) - Enables the GSC receive error interrupt. IEN1.2 (EDMA0) - Enables the DMA done interrupt for channel 0. IEN1.3 (EGSTV) - Enables the GSC valid transmi
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KS152JB Universal Communications Controller Technical Specifications The interrupt flags are sampled in S5P2 of every machine cycle. In the next machine cycle, the sampled interrupts are polled and their priority is resolved. If certain conditions are met then the hardware will execute an internally generated LCALL instruction which will vector the process to the appropriate interrupt vector address. The conditions for generating the LCALL are 1. An interrupt of equal or higher priority is not cu
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KS152JB Universal Communications Controller Technical Specifications Table 5: Interrupt Interrupt Priority Priority Priority Vector Symbolic Symbolic sequence address name Address name Name 8 IPN1.4 PDMA1 IEN1.4 EDMA1 53H 9 IP.3 PT1 1E.3 ET1 1BH 10 IPN1.5 PGSTE IEN1.5 EGSTE 4BH 11 IP.4 PS IE.4 ES 23H Execution continues from the vectored address till an RETI instruction is executed. On execution of the RETI instruction the processor pops the Stack and loads the PC with the contents at the top of
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KS152JB Universal Communications Controller Technical Specifications values are polled only in the next machine cycle. If a request is active and all three conditions are met, then the hardware generated LCALL is executed. This call itself takes two machine cycles to be completed. Thus there is a minimum time of three machine cycles between the interrupt flag being set and the interrupt service routine being executed. A longer response time should be anticipated if any of the three conditions are
