Resumen del contenido incluido en la página 1
MultiProcessor
Specification
Version 1.4
May 1997
Resumen del contenido incluido en la página 2
THIS SPECIFICATION IS PROVIDED "AS IS" WITH NO WARRANTIES WHATSOEVER, INCLUDING ANY WARRANTY OF MERCHANTABILITY, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY WARRANTY OTHERWISE ARISING OUT OF ANY PROPOSAL, SPECIFICATION OR SAMPLE. A license is hereby granted to copy and reproduce this specification for internal use only. No other license, express or implied, by estoppel or otherwise, to any other intellectual property rights is granted herein. Intel disclaims all liability, including liability f
Resumen del contenido incluido en la página 3
Revision History Revision Revision History Date Pre-release Version 1.0. Formerly called “PC+MP Specification” 10/27/93 -001 Version 1.1. Resolves conflicts with MCA-based systems. The following 4/11/94 changes have been made: 1. Two MP feature information bytes were moved from the BIOS System Configuration Table to the RESERVED area of the MP Floating Pointer Structure. 2. If the MP Floating Pointer Structure is present, it indicates that the system is MP-compliant, in accordance with this
Resumen del contenido incluido en la página 4
Resumen del contenido incluido en la página 5
Table of Contents Chapter 1 Introduction 1.1 Goals ........................................................................................................ 1-1 1.2 Features of the Specification .................................................................... 1-2 1.3 Scope........................................................................................................ 1-2 1.4 Target Audience ....................................................................................... 1-3 1.
Resumen del contenido incluido en la página 6
Contents 3.6.6 APIC Identification ..................................................................... 3-13 3.6.7 APIC Interval Timers.................................................................. 3-13 3.6.8 Multiple I/O APIC Configurations ............................................... 3-13 3.7 RESET Support ...................................................................................... 3-14 3.7.1 System-wide RESET .................................................................
Resumen del contenido incluido en la página 7
Contents Appendix A System BIOS Programming Guidelines A.1 BIOS Post Initialization ............................................................................A-1 A.2 Controlling the Application Processors ....................................................A-2 A.3 Programming the APIC for Virtual Wire Mode .........................................A-2 A.4 Constructing the MP Configuration Table................................................A-4 Appendix B Operating System Programming Guidelin
Resumen del contenido incluido en la página 8
Contents Figures 1-1. Conceptual Overview...................................................................... 1-1 1-2. Memory Layout Conventions .......................................................... 1-4 2-1. Multiprocessor System Architecture................................................ 2-2 2-2. APIC Configuration ......................................................................... 2-3 3-1. System Memory Address Map........................................................ 3-2 3-2.
Resumen del contenido incluido en la página 9
Contents 4-6. Feature Flags from CPUID Instruction............................................ 4-9 4-7. Bus Entry Fields............................................................................ 4-10 4-8. Bus Type String Values................................................................. 4-11 4-9. I/O APIC Entry Fields .................................................................... 4-12 4-10. I/O Interrupt Entry Fields............................................................... 4-1
Resumen del contenido incluido en la página 10
Resumen del contenido incluido en la página 11
1 Introduction The MultiProcessor Specification, hereafter known as the “MP specification,” defines an enhancement to the standard to which PC manufacturers design DOS-compatible systems. MP-capable operating systems will be able to run without special customization on multiprocessor systems that comply with this specification. End users who purchase a compliant multiprocessor system will be able to run their choice of operating systems. The MP specification covers PC/AT-compatible MP platform
Resumen del contenido incluido en la página 12
MultiProcessor Specification 1.2 Features of the Specification The MP specification includes the following features: • A multiprocessor extension to the PC/AT platform that runs all existing uniprocessor shrink- wrapped binaries, as well as MP binaries. • Support for symmetric multiprocessing with one or more processors that are Intel architecture ® instruction set compatible, such as the CPUs in the Intel486™ and the Pentium processor family. • Support for symmetric I/O interrupt handling with
Resumen del contenido incluido en la página 13
Introduction In addition to the hardware requirements, this document also specifies MP features that are visible to the BIOS and operating system. However, it is important to understand that as hardware technology progresses, the functions performed by the BIOS may change in accordance with the hardware technology. ONLY THE INTERFACE TO THE OPERATING SYSTEM LEVEL IS EXPECTED TO REMAIN CONSTANT. This specification does not address issues relating to the processor's System Management Mode (SMM).
Resumen del contenido incluido en la página 14
MultiProcessor Specification 1.6 Conventions Used in This Document Signal names that are followed by the character # represent active low signals. For example, FERR# is active when at its low-voltage state. Throughout this document, the Intel 82489DX APIC is referred to as the “discrete APIC.” The term “integrated APIC” is used to refer to an APIC integrated with other system components, such as the Pentium 735\90 and 815\100 processors. This specification uses the term APIC to refer to both d
Resumen del contenido incluido en la página 15
2 System Overview In the realm of multiprocessor architectures, there are several conceptual models for tying together computing elements, and there are a variety of interconnection schemes and details of implementation. Figure 2-1 shows the general structure of a design based on the MP specification. The MP specification’s model of multiprocessor systems incorporates a tightly-coupled, shared- memory architecture with a distributed interprocessor and I/O interrupt capability. It is fully sym
Resumen del contenido incluido en la página 16
MultiProcessor Specification CPU CPU CPU HIGH-BANDWIDTH MEMORY BUS ICC BUS APIC APIC SHARED GRAPHICS MEMORY FRAME I/O I/O MODULE BUFFER INTERFACE INTERFACE APIC ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER ICC INTERRUPT CONTROLLER I/O EXPANSION BUS I/O EXPANSION BUS COMMUNICATIONS Figure 2-1. Multiprocessor System Architecture 2.1 Hardware Overview The MP specification defines a system architecture based on the following hardware components: • One or more processors that are Intel architecture
Resumen del contenido incluido en la página 17
System Overview only during the initialization and shutdown processes. The BSP is responsible for initializing the system and for booting the operating system; APs are activated only after the operating system is up and running. CPU1 is designated as the BSP. CPU2, CPU3, and so on, are designated as the APs. BSP AP1 AP2 CPU 1 CPU 2 CPU 3 LOCAL LOCAL LOCAL APIC APIC APIC 1 2 3 ICC BUS 0 0 1 1 2 2 3 3 4 4 5 5 6 6 INTERRUPT INTERRUPT 7 I/O I/O 7 REQUESTS REQUESTS 8 8 APIC APIC 9 9 10 10 11 11 12
Resumen del contenido incluido en la página 18
MultiProcessor Specification The local APIC units also provide interprocessor interrupts (IPIs), which allow any processor to interrupt any other processor or set of processors. There are several types of IPIs. Among them, the INIT IPI and the STARTUP IPI are specifically designed for system startup and shutdown. Each local APIC has a Local Unit ID Register and each I/O APIC has an I/O Unit ID Register. The ID serves as a physical name for each APIC unit. It is used by software to specify des
Resumen del contenido incluido en la página 19
System Overview 2.2 BIOS Overview A BIOS functions as an insulator between the hardware on one hand, and the operating system and applications software on the other. A standard uniprocessor BIOS performs the following functions: • Tests system components. • Builds configuration tables to be used by the operating system. • Initializes the processor and the rest of the system to a known state. • Provides run-time device-oriented services. For a multiprocessor system, the BIOS may perform the foll
Resumen del contenido incluido en la página 20
