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MCF548x Reference Manual
Devices Supported:
MCF5485 MCF5482
MCF5484 MCF5481
MCF5483 MCF5480
Document Number: MCF5485RM
Rev. 3
01/2006
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How to Reach Us: Home Page: www.freescale.com E-mail: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com Information in this document is provided solely to enable system and Europe, Middle East, and Africa: software implementers to use Freescale Semiconductor products. There are Freescale Halbleiter Deutschland GmbH no expr
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1 Overview 2 Signal Descriptions 3 ColdFire Core 4 Enhanced Multiply-Accumulate Unit (EMAC) 5 Memory Management Unit (MMU) 6 Floating-Point Unit (FPU) 7 Local Memory 8 Debug Support 9 System Integration Unit (SIU) 10 Internal Clocks and Bus Architecture 11 General Purpose Timers (GPT) Slice Timers (SLT) 12 Interrupt Controller (INTC) 13 Edge Port Module (EPORT) 14 General Purpose I/O (GPIO) 15 16 System SRAM 17 FlexBus 18 SDRAM Controller (SDRAMC) 19 PCI Bus Controller (PCI) 20 PCI Bus Arbiter (
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1 Overview 2 Signal Descriptions 3 ColdFire Core 4 Enhanced Multiply-Accumulate Unit (EMAC) 5 Memory Management Unit (MMU) 6 Floating-Point Unit (FPU) 7 Local Memory 8 Debug Support 9 System Integration Unit (SIU) 10 Internal Clocks and Bus Architecture 11 General Purpose Timers (GPT) 12 Slice Timers (SLT) 13 Interrupt Controller (INTC) 14 Edge Port Module (EPORT) 15 General Purpose I/O (GPIO) 16 System SRAM 17 FlexBus 18 SDRAM Controller (SDRAMC) 19 PCI Bus Controller (PCI) 20 PCI Bus Arbiter (
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Contents Page Paragraph Title Number Number Chapter 1 Overview 1.1 MCF548x Family Overview ........................................................................................... 1-1 1.2 MCF548x Block Diagram ..............................................................................................1-2 1.3 MCF548x Family Products ............................................................................................. 1-3 1.4 MCF548x Family Features .................................
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Contents Page Paragraph Title Number Number 2.2.1.4 Read/Write (R/W) ................................................................................................. 2-17 2.2.1.5 Transfer Burst (TBST) .......................................................................................... 2-17 2.2.1.6 Transfer Size (TSIZ[1:0]) ..................................................................................... 2-17 2.2.1.7 Byte Selects (BE/BWE[3:0]) ..........................................
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Contents Page Paragraph Title Number Number 2.2.5.1 Reset In (RSTI) ..................................................................................................... 2-22 2.2.5.2 Reset Out (RSTO) ................................................................................................. 2-22 2.2.5.3 Clock In (CLKIN) ................................................................................................. 2-22 2.2.6 Reset Configuration Pins ......................................
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Contents Page Paragraph Title Number Number 2 2.2.11 I C I/O Signals .......................................................................................................... 2-27 2.2.11.1 Serial Clock (SCL) ...............................................................................................2-28 2.2.11.2 Serial Data (SDA) ................................................................................................. 2-28 2.2.12 PSC Module Signals ...................................
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Contents Page Paragraph Title Number Number Chapter 3 ColdFire Core 3.1 Core Overview ................................................................................................................ 3-1 3.2 Features ........................................................................................................................... 3-1 3.2.1 Enhanced Pipelines ..................................................................................................... 3-2 3.2.1.1 Instruction Fet
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Contents Page Paragraph Title Number Number 3.7.4 Miscellaneous Instruction Execution Timing ........................................................... 3-32 3.7.5 Branch Instruction Execution Timing ....................................................................... 3-33 3.7.6 EMAC Instruction Execution Times ........................................................................ 3-34 3.7.7 FPU Instruction Execution Times ....................................................................
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Contents Page Paragraph Title Number Number 5.2.3.9 Changes to ACRs and CACR ................................................................................. 5-5 5.2.3.10 ACR Address Improvements .................................................................................. 5-6 5.2.3.11 Supervisor Protection .............................................................................................. 5-7 5.3 Debugging in a Virtual Environment ...............................................
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Contents Page Paragraph Title Number Number 6.2.3.5 Denormalized Numbers .......................................................................................... 6-5 6.3 Register Definition .......................................................................................................... 6-7 6.3.1 Floating-Point Data Registers (FP0–FP7) .................................................................. 6-7 6.3.2 Floating-Point Control Register (FPCR) ...................................
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Contents Page Paragraph Title Number Number 7.8.1 Cache Line States: Invalid, Valid-Unmodified, and Valid-Modified ......................... 7-8 7.8.2 The Cache at Start-Up ................................................................................................. 7-8 7.9 Cache Operation ........................................................................................................... 7-10 7.9.1 Caching Modes ........................................................................
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Contents Page Paragraph Title Number Number 8.4.5 Address Attribute Trigger Registers (AATR, AATR1) ............................................ 8-16 8.4.6 Trigger Definition Register (TDR) ........................................................................... 8-17 8.4.7 Program Counter Breakpoint and Mask Registers (PBRn, PBMR) ......................... 8-20 8.4.8 Address Breakpoint Registers (ABLR/ABLR1, ABHR/ABHR1) ...........................8-21 8.4.9 Data Breakpoint and Mask Registers
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Contents Page Paragraph Title Number Number 9.3.1.4 JTAG Device Identification Number (JTAGID) .................................................... 9-5 Chapter 10 Internal Clocks and Bus Architecture 10.1 Introduction ................................................................................................................... 10-1 10.1.1 Block Diagram .......................................................................................................... 10-1 10.1.2 Clocking Overview .
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Contents Page Paragraph Title Number Number 11.1.1 Overview ................................................................................................................... 11-1 11.1.2 Modes of Operation ..................................................................................................11-1 11.2 External Signals ............................................................................................................ 11-2 11.3 Memory Map/Register Definition ..................
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Contents Page Paragraph Title Number Number Chapter 14 Edge Port Module (EPORT) 14.1 Introduction ................................................................................................................... 14-1 14.2 Interrupt/General-Purpose I/O Pin Descriptions ........................................................... 14-1 14.3 Memory Map/Register Definition ................................................................................ 14-2 14.3.1 Memory Map ......................
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Contents Page Paragraph Title Number Number 15.4 Functional Description ................................................................................................ 15-32 15.4.1 Overview ................................................................................................................. 15-32 Chapter 16 32-Kbyte System SRAM 16.1 Introduction ................................................................................................................... 16-1 16.1.1 Block Dia
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Contents Page Paragraph Title Number Number 17.5.1.2 Global Chip-Select Operation ............................................................................... 17-6 17.5.2 Chip-Select Registers ................................................................................................ 17-7 17.5.2.1 Chip-Select Address Registers (CSAR0–CSAR5) ............................................... 17-8 17.5.2.2 Chip-Select Mask Registers (CSMR0–CSMR5) ..............................................
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Contents Page Paragraph Title Number Number 18.3.13 SDR SDRAM Data Strobe (SDRDQS) .................................................................... 18-4 18.3.14 SDRAM Memory Supply (SDVDD) ........................................................................ 18-4 18.3.15 SDRAM Reference Voltage (VREF) ....................................................................... 18-4 18.4 Interface Recommendations ..................................................................................
