Resumen del contenido incluido en la página 1
STK12C68-5 (SMD5962-94599)
64 Kbit (8K x 8) AutoStore nvSRAM
Features Functional Description
■ 35 ns and 55 ns access times The Cypress STK12C68-5 is a fast static RAM with a nonvol-
atile element in each memory cell. The embedded nonvolatile
■ Hands off automatic STORE on power down with external
elements incorporate QuantumTrap technology producing the
68 µF capacitor
world’s most reliable nonvolatile memory. The SRAM provides
unlimited read and write cycles, while independent nonvolatile
■ S
Resumen del contenido incluido en la página 2
STK12C68-5 (SMD5962-94599) Pinouts Figure 1. Pin Diagram - 28-Pin DIP Figure 2. Pin Diagram - 28-Pin LLC Pin Definitions Pin Name Alt IO Type Description A –A Input Address Inputs. Used to select one of the 8,192 bytes of the nvSRAM. 0 12 DQ -DQ Input or Output Bidirectional Data IO Lines. Used as input or output lines depending on operation. 0 7 Input Write Enable Input, Active LOW. When the chip is enabled and WE is LOW, data on the IO WE W pins is written to the specific address location.
Resumen del contenido incluido en la página 3
STK12C68-5 (SMD5962-94599) During normal operation, the device draws current from V to Device Operation CC charge a capacitor connected to the V pin. This stored CAP charge is used by the chip to perform a single STORE operation. The STK12C68-5 nvSRAM is made up of two functional compo- If the voltage on the V pin drops below V , the part nents paired in the same physical cell. These are an SRAM CC SWITCH automatically disconnects the V pin from V . A STORE memory cell and a nonvolatile QuantumT
Resumen del contenido incluido en la página 4
STK12C68-5 (SMD5962-94599) Figure 4. AutoStore Inhibit Mode During any STORE operation, regardless of how it is initiated, the STK12C68-5 continues to drive the HSB pin LOW, releasing it only when the STORE is complete. After completing the STORE operation, the STK12C68-5 remains disabled until the HSB pin returns HIGH. If HSB is not used, it is left unconnected. Hardware RECALL (Power Up) During power up or after any low power condition (V < CC V ), an internal
Resumen del contenido incluido en la página 5
STK12C68-5 (SMD5962-94599) 4. Read address 0x1FFF, Valid READ Figure 5. Current Versus Cycle Time (Read) 5. Read address 0x10F0, Valid READ 6. Read address 0x0F0E, Initiate RECALL cycle Internally, RECALL is a two step procedure. First, the SRAM data is cleared; then, the nonvolatile information is transferred into the SRAM cells. After the t cycle time, the SRAM is again RECALL ready for Read and Write operations. The RECALL operation does not alter the data in the nonvolatile elements. The no
Resumen del contenido incluido en la página 6
STK12C68-5 (SMD5962-94599) ■ Power up boot firmware routines must rewrite the nvSRAM Best Practices into the desired state. While the nvSRAM is shipped in a preset state, best practice is to again rewrite the nvSRAM nvSRAM products have been used effectively for over 15 into the desired state as a safeguard against events that years. While ease-of-use is one of the product’s main system might flip the bit inadvertently (program bugs, incoming values, experience gained working with hundreds
Resumen del contenido incluido en la página 7
STK12C68-5 (SMD5962-94599) Voltage on DQ or HSB .......................–0.5V to Vcc + 0.5V Maximum Ratings 0-7 Power Dissipation.......................................................... 1.0W Exceeding maximum ratings may shorten the useful life of the DC output Current (1 output at a time, 1s duration) .... 15 mA device. These user guidelines are not tested. Storage Temperature ................................. –65 °C to +150 °C Operating Range Temperature under Bias ..........................
Resumen del contenido incluido en la página 8
STK12C68-5 (SMD5962-94599) Data Retention and Endurance Parameter Description Min Unit DATA Data Retention 100 Years R NV Nonvolatile STORE Operations 1,000 K C Capacitance [6] In the following table, the capacitance parameters are listed. Parameter Description Test Conditions Max Unit C Input Capacitance T = 25 °C, f = 1 MHz, 8pF IN A V = 0 to 3.0 V CC C Output Capacitance 7pF OUT Thermal Resistance [6] In the following table, the thermal resistance parameters are listed. Parameter Description
Resumen del contenido incluido en la página 9
STK12C68-5 (SMD5962-94599) AC Switching Characteristics SRAM Read Cycle Parameter 35 ns 55 ns Description Unit Cypress Alt Min Max Min Max Parameter t t Chip Enable Access Time 35 55 ns ACE ELQV [7] t t t Read Cycle Time 35 55 ns RC AVAV, ELEH [8] t t Address Access Time 35 55 ns AA AVQV t t Output Enable to Data Valid 15 35 ns DOE GLQV [8] t t Output Hold After Address Change 5 5 ns OHA AXQX [9] t t Chip Enable to Output Active 5 5 ns LZCE ELQX [9] t t Chip Disable to Output Inactive 10 12 ns
Resumen del contenido incluido en la página 10
STK12C68-5 (SMD5962-94599) SRAM Write Cycle Parameter 35 ns 55 ns Description Unit Cypress Alt Min Max Min Max Parameter t t Write Cycle Time 35 55 ns WC AVAV t t t Write Pulse Width 25 45 ns PWE WLWH, WLEH t t t Chip Enable To End of Write 25 45 ns SCE ELWH, ELEH t t t Data Setup to End of Write 12 25 ns SD DVWH, DVEH t t t Data Hold After End of Write 0 0 ns HD WHDX, EHDX t t t Address Setup to End of Write 25 45 ns AW AVWH, AVEH t t t Address Setup to Start of Write 0 0 ns SA AVWL, AVEL t t
Resumen del contenido incluido en la página 11
STK12C68-5 (SMD5962-94599) AutoStore or Power Up RECALL STK12C68-5 Parameter Alt Description Unit Min Max [13] t Power up RECALL Duration 550 μs t RESTORE HRECALL [14, 15, 16] t STORE Cycle Duration 10 ms t HLHZ STORE [9, 15] t t Time Allowed to Complete SRAM Cycle 1 μs t HLQZ , BLQZ DELAY V Low Voltage Trigger Level 4.0 4.5 V SWITCH V Low Voltage Reset Level 3.9 V RESET t V Rise Time 150 μs VCCRISE CC [11] Low Voltage Trigger (V ) to HSB Low 300 ns t SWITCH VSBL Switching Waveform Figure 1
Resumen del contenido incluido en la página 12
STK12C68-5 (SMD5962-94599) Software Controlled STORE/RECALL Cycle [18] The software controlled STORE/RECALL cycle follows. 35 ns 55 ns Parameter Alt Description Unit Min Max Min Max [14] t t STORE/RECALL Initiation Cycle Time 35 55 ns RC AVAV [17] t t Address Setup Time 0 0 ns SA AVEL [17] t t Clock Pulse Width 25 30 ns CW ELEH [17] t t Address Hold Time 20 20 ns HACE ELAX t RECALL Duration 20 20 μs RECALL Switching Waveform [18] Figure 13. CE Controlled Software STORE/RECALL Cycle t t RC RC
Resumen del contenido incluido en la página 13
STK12C68-5 (SMD5962-94599) Hardware STORE Cycle STK12C68-5 Parameter Alt Description Unit Min Max [9, 14] t STORE Cycle Duration 10 ms t HLHZ STORE [14, 19] t t Hardware STORE High to Inhibit Off 700 ns t RECOVER, HHQX DHSB t t Hardware STORE Pulse Width 15 ns PHSB HLHX t Hardware STORE Low to STORE Busy 300 ns HLBL Switching Waveform Figure 14. Hardware STORE Cycle Note 19. t is only applicable after t is complete. DHSB STORE Document Number: 001-51026 Rev. ** Page 13 of 18 [+] Feedback
Resumen del contenido incluido en la página 14
STK12C68-5 (SMD5962-94599) Part Numbering Nomenclature STK12C68 - 5 C 35 M Temperature Range: M - Military (-55 to 125°C) Speed: 35 - 35 ns 55 - 55 ns Package: C = Ceramic 28-pin 300 mil DIP (gold lead finish) K = Ceramic 28-pin 300 mil DIP (Solder dip finish) L = Ceramic 28-pin LLC Retention / Endurance 5 5 = Military (10 years or 10 cycles) SMD5962 - 94599 01 MX X Lead Finish A = Solder DIP lead finish C = Gold lead DIP finish X = Lead finish “A” or “C” is acceptable Case Outline X = Cera
Resumen del contenido incluido en la página 15
STK12C68-5 (SMD5962-94599) Ordering Information Speed (ns) Ordering Code Package Diagram Package Type Operating Range 35 STK12C68-5C35M 001-51695 28-pin CDIP (300 mil) Military STK12C68-5K35M 001-51695 28-pin CDIP (300 mil) STK12C68-5L35M 001-51696 28-pin LCC (350 mil) 55 STK12C68-5C55M 001-51695 28-pin CDIP (300 mil) STK12C68-5K55M 001-51695 28-pin CDIP (300 mil) STK12C68-5L55M 001-51696 28-pin LCC (350 mil) The above table contains Final information. Contact your local Cypress sales represent
Resumen del contenido incluido en la página 16
STK12C68-5 (SMD5962-94599) Package Diagrams Figure 15. 28-Pin (300-Mil) Side Braze DIL (001-51695) 001-51695 ** Document Number: 001-51026 Rev. ** Page 16 of 18 [+] Feedback
Resumen del contenido incluido en la página 17
STK12C68-5 (SMD5962-94599) Package Diagrams (continued) Figure 16. 28-Pad (350-Mil) LCC (001-51696) 1. ALL DIMENSION ARE IN INCHES AND MILLIMETERS [MIN/MAX] 2. JEDEC 95 OUTLINE# MO-041 3. PACKAGE WEIGHT : TBD 001-51696 ** Document Number: 001-51026 Rev. ** Page 17 of 18 [+] Feedback
Resumen del contenido incluido en la página 18
STK12C68-5 (SMD5962-94599) Document History Page Document Title: STK12C68-5 (SMD5962-94599), 64 Kbit (8K x 8) AutoStore nvSRAM Document Number: 001-51026 Orig. of Submission Rev ECN No. Description of Change Change Date ** 2666844 GVCH/PYRS 03/02/09 New data sheet Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit
