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CY7C1392CV18, CY7C1992CV18
CY7C1393CV18, CY7C1394CV18
18-Mbit DDR-II SIO SRAM 2-Word
Burst Architecture
Features Functional Description
■ 18-Mbit density (2M x 8, 2M x 9, 1M x 18, 512K x 36) The CY7C1392CV18, CY7C1992CV18, CY7C1393CV18, and
CY7C1394CV18 are 1.8V Synchronous Pipelined SRAMs,
■ 300 MHz clock for high bandwidth
equipped with Double Data Rate Separate IO (DDR-II SIO)
■ 2-word burst for reducing address bus frequency
architecture. The DDR-II SIO consists of two separate ports: the
r
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1M x 8 Array 1M x 9 Array 1M x 8 Array 1M x 9 Array CY7C1392CV18, CY7C1992CV18 CY7C1393CV18, CY7C1394CV18 Logic Block Diagram (CY7C1392CV18) 8 D [7:0] Write Write Data Reg Data Reg 20 Address A (19:0) Register LD K Control R/W CLK Logic K Gen. C DOFF Read Data Reg. C CQ 16 R/W 8 CQ Reg. Reg. V 8 REF Control 8 Logic LD 8 Reg. Q 8 [7:0] NWS [1:0] Logic Block Diagram (CY7C1992CV18) 9 D [8:0] Write Write Data Reg Data Reg 20 Address A (19:0) Register LD K Control R/W CLK Logic K Gen. C DOFF Read Dat
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512K x 18 Array 256K x 18 Array 512K x 18 Array 256K x 18 Array CY7C1392CV18, CY7C1992CV18 CY7C1393CV18, CY7C1394CV18 Logic Block Diagram (CY7C1393CV18) 18 D [17:0] Write Write Data Reg Data Reg 19 Address A (18:0) Register LD K Control R/W CLK Logic K Gen. C DOFF Read Data Reg. C CQ 36 R/W 18 CQ Reg. Reg. V 18 REF Control Logic 18 LD Reg. 18 Q 18 [17:0] BWS [1:0] Logic Block Diagram (CY7C1394CV18) 36 D [35:0] Write Write Data Reg Data Reg 18 Address A (17:0) Register LD K Control R/W CLK Logic
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CY7C1392CV18, CY7C1992CV18 CY7C1393CV18, CY7C1394CV18 Pin Configuration [1] The Pin Configuration for CY7C1392CV18, CY7C1992CV18, CY7C1393CV18, and CY7C1394CV18 follows. 165-Ball FBGA (13 x 15 x 1.4 mm) Pinout CY7C1392CV18 (2M x 8) 1 2 3 4 5 6 7 8 9 10 11 A CQ NC/72M A R/W NWS K NC/144M LD A NC/36M CQ 1 B NC NC NC A NC/288M K NWS ANC NC Q3 0 C NC NC NC V AAA V NC NC D3 SS SS D NC D4 NC V V V V V NC NC NC SS SS SS SS SS E NC NC Q4 V V V V V NC D2 Q2 DDQ SS SS SS DDQ F NC NC NC V V V V V NC NC
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CY7C1392CV18, CY7C1992CV18 CY7C1393CV18, CY7C1394CV18 Pin Configuration (continued) [1] The Pin Configuration for CY7C1392CV18, CY7C1992CV18, CY7C1393CV18, and CY7C1394CV18 follows. 165-Ball FBGA (13 x 15 x 1.4 mm) Pinout CY7C1393CV18 (1M x 18) 1 2 3 4 5 6 7 8 9 10 11 A CQ NC/144M NC/36M R/W BWS K NC/288M LD A NC/72M CQ 1 B NC Q9 D9 A NC K BWS ANC NC Q8 0 C NC NC D10 V AAA V NC Q7 D8 SS SS D NC D11 Q10 V V V V V NC NC D7 SS SS SS SS SS E NC NC Q11 V V V V V NC D6 Q6 DDQ SS SS SS DDQ F NC Q12
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CY7C1392CV18, CY7C1992CV18 CY7C1393CV18, CY7C1394CV18 Pin Definitions Pin Name IO Pin Description D Input- Data input signals. Sampled on the rising edge of K and K clocks during valid write operations. [x:0] CY7C1392CV18 - D Synchronous [7:0] CY7C1992CV18 - D [8:0] CY7C1393CV18 - D [17:0] CY7C1394CV18 - D [35:0] LD Input- Synchronous load. This input is brought LOW when a bus cycle sequence is defined. This definition Synchronous includes address and read/write direction. All transactions op
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CY7C1392CV18, CY7C1992CV18 CY7C1393CV18, CY7C1394CV18 Pin Definitions (continued) Pin Name IO Pin Description CQ Echo Clock CQ is referenced with respect to C. This is a free-running clock and is synchronized to the input clock for output data (C) of the DDR-II. In the single clock mode, CQ is generated with respect to K. The timings for the echo clocks is shown in the Switching Characteristics on page 23. CQ Echo Clock CQ is referenced with respect to C. This is a free-running clock and is s
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CY7C1392CV18, CY7C1992CV18 CY7C1393CV18, CY7C1394CV18 bits of data can be transferred into the device on every rising Functional Overview edge of the input clocks (K and K). The CY7C1392CV18, CY7C1992CV18, CY7C1393CV18, and When Write access is deselected, the device ignores all inputs CY7C1394CV18 are synchronous pipelined Burst SRAMs after the pending write operations are completed. equipped with a DDR-II Separate IO interface, which operates with a read latency of one and half cycles when D
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CY7C1392CV18, CY7C1992CV18 CY7C1393CV18, CY7C1394CV18 synchronized to the output clock of the DDR-II. In the single clock DLL is locked after 1024 cycles of stable clock. The DLL can also mode, CQ is generated with respect to K and CQ is generated be reset by slowing or stopping the input clocks K and K for a with respect to K. The timing for the echo clocks is shown in minimum of 30 ns. However, it is not necessary to reset the DLL Switching Characteristics on page 23. to lock it to the desired
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CY7C1392CV18, CY7C1992CV18 CY7C1393CV18, CY7C1394CV18 Truth Table [2, 3, 4, 5, 6, 7] The truth table for CY7C1392CV18, CY7C1992CV18, CY7C1393CV18, and CY7C1394CV18 follows. Operation K LD R/W DQ DQ L-H L L D(A + 0) at K(t + 1)↑ D(A + 1) at K(t + 1)↑ Write Cycle: Load address; wait one cycle; input write data on consecutive K and K rising edges. Read Cycle: L-H L H Q(A + 0) at C(t + 1)↑ Q(A + 1) at C(t + 2)↑ Load address; wait one and a half cycle; read data on consecutive C and C rising edges
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CY7C1392CV18, CY7C1992CV18 CY7C1393CV18, CY7C1394CV18 Write Cycle Descriptions [2, 8] The write cycle description table for CY7C1992CV18 follows. BWS K K Comments 0 L L–H – During the data portion of a write sequence, the single byte (D ) is written into the device. [8:0] ) is written into the device. L – L–H During the data portion of a write sequence, the single byte (D [8:0] H L–H – No data is written into the device during this portion of a write operation. H – L–H No data is written into t
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CY7C1392CV18, CY7C1992CV18 CY7C1393CV18, CY7C1394CV18 Instruction Register IEEE 1149.1 Serial Boundary Scan (JTAG) Three-bit instructions can be serially loaded into the instruction These SRAMs incorporate a serial boundary scan Test Access register. This register is loaded when it is placed between the TDI Port (TAP) in the FBGA package. This part is fully compliant with and TDO pins, as shown in TAP Controller Block Diagram on IEEE Standard #1149.1-2001. The TAP operates using JEDEC page 15. U
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CY7C1392CV18, CY7C1992CV18 CY7C1393CV18, CY7C1394CV18 IDCODE BYPASS The IDCODE instruction loads a vendor-specific, 32-bit code into When the BYPASS instruction is loaded in the instruction register the instruction register. It also places the instruction register and the TAP is placed in a Shift-DR state, the bypass register is between the TDI and TDO pins and shifts the IDCODE out of the placed between the TDI and TDO pins. The advantage of the device when the TAP controller enters the Shift-D
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CY7C1392CV18, CY7C1992CV18 CY7C1393CV18, CY7C1394CV18 TAP Controller State Diagram [9] The state diagram for the TAP controller follows. TEST-LOGIC 1 RESET 0 1 1 1 TEST-LOGIC/ SELECT SELECT 0 IDLE DR-SCAN IR-SCAN 0 0 1 1 CAPTURE-DR CAPTURE-IR 0 0 0 0 SHIFT-DR SHIFT-IR 1 1 1 1 EXIT1-DR EXIT1-IR 0 0 0 0 PAUSE-DR PAUSE-IR 1 1 0 0 EXIT2-DR EXIT2-IR 1 1 UPDATE-IR UPDATE-DR 1 1 0 0 Note 9. The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document #: 001-07162 Rev. *C
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CY7C1392CV18, CY7C1992CV18 CY7C1393CV18, CY7C1394CV18 TAP Controller Block Diagram 0 Bypass Register 2 1 0 Selection Selection TDI TDO Instruction Register Circuitry Circuitry 31 30 29 . . 2 1 0 Identification Register . 106 . . . 2 1 0 Boundary Scan Register TCK TAP Controller TMS TAP Electrical Characteristics [10, 11, 12] Over the Operating Range Parameter Description Test Conditions Min Max Unit V Output HIGH Voltage I = −2.0 mA 1.4 V OH1 OH Output HIGH Voltage I = −100 μA1.6 V V OH2 OH
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CY7C1392CV18, CY7C1992CV18 CY7C1393CV18, CY7C1394CV18 TAP AC Switching Characteristics [13, 14] Over the Operating Range Parameter Description Min Max Unit t TCK Clock Cycle Time 50 ns TCYC t TCK Clock Frequency 20 MHz TF t TCK Clock HIGH 20 ns TH t TCK Clock LOW 20 ns TL Setup Times t TMS Setup to TCK Clock Rise 5 ns TMSS t TDI Setup to TCK Clock Rise 5 ns TDIS t Capture Setup to TCK Rise 5 ns CS Hold Times t TMS Hold after TCK Clock Rise 5 ns TMSH t TDI Hold after Clock Rise 5 ns TDIH t Capt
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CY7C1392CV18, CY7C1992CV18 CY7C1393CV18, CY7C1394CV18 Identification Register Definitions Value Instruction Field Description CY7C1392CV18 CY7C1992CV18 CY7C1393CV18 CY7C1394CV18 Revision Number 000 000 000 000 Version number. (31:29) Cypress Device ID 11010100010000101 11010100010001101 11010100010010101 11010100010100101 Defines the type of (28:12) SRAM. Cypress JEDEC ID 00000110100 00000110100 00000110100 00000110100 Allows unique (11:1) identification of SRAM vendor. ID Register 1111 Indi
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CY7C1392CV18, CY7C1992CV18 CY7C1393CV18, CY7C1394CV18 Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID 0 6R 28 10G 56 6A 84 2J 1 6P29 9G 57 5B85 3K 2 6N 30 11F 58 5A 86 3J 3 7P 31 11G 59 4A 87 2K 4 7N32 9F 60 5C88 1K 5 7R 33 10F 61 4B 89 2L 6 8R 34 11E 62 3A 90 3L 7 8P 35 10E 63 1H 91 1M 8 9R 36 10D 64 1A 92 1L 9 11P 37 9E 65 2B 93 3N 10 10P 38 10C 66 3B 94 3M 11 10N 39 11D 67 1C 95 1N 12 9P 40 9C 68 1B 96 2M 13 10M 41 9D 69 3D 97 3P 14 11N 42 11B 70 3C 98 2N 15 9M 43
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~ ~ CY7C1392CV18, CY7C1992CV18 CY7C1393CV18, CY7C1394CV18 DLL Constraints Power Up Sequence in DDR-II SRAM ■ DLL uses K clock as its synchronizing input. The input must DDR-II SRAMs must be powered up and initialized in a have low phase jitter, which is specified as t . KC Var predefined manner to prevent undefined operations. ■ The DLL functions at frequencies down to 120 MHz. Power Up Sequence ■ If the input clock is unstable and the DLL is enabled, then the ■ Apply power and drive DOFF eith
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CY7C1392CV18, CY7C1992CV18 CY7C1393CV18, CY7C1394CV18 Current into Outputs (LOW) ........................................ 20 mA Maximum Ratings Static Discharge Voltage (MIL-STD-883, M. 3015).. > 2001V Exceeding maximum ratings may impair the useful life of the Latch-up Current ................................................... > 200 mA device. These user guidelines are not tested. Storage Temperature ................................. –65°C to +150°C Operating Range Ambient Temperature with Pow
