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CY7C1360C
CY7C1362C
9-Mbit (256K x 36/512K x 18) Pipelined SRAM
[1]
Features Functional Description
• Supports bus operation up to 250 MHz The CY7C1360C/CY7C1362C SRAM integrates 256K x 36
and 512K x 18 SRAM cells with advanced synchronous
• Available speed grades are 250, 200, and 166 MHz
peripheral circuitry and a two-bit counter for internal burst
• Registered inputs and outputs for pipelined operation
operation. All synchronous inputs are gated by registers
controlled by a positive-edge-tr
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CY7C1360C CY7C1362C . Logic Block Diagram – CY7C1360C (256K x 36) A0, A1, A ADDRESS REGISTER 2 A[1:0] MODE ADV Q1 BURST CLK COUNTER CLR AND Q0 LOGIC ADSC ADSP DQD ,DQPD DQD ,DQPD BYTE BWD BYTE WRITE REGISTER WRITE DRIVER DQC ,DQPC DQC ,DQPC BYTE BWC BYTE OUTPUT WRITE DRIVER WRITE REGISTER OUTPUT MEMORY DQs SENSE BUFFERS ARRAY REGISTERS AMPS DQPA DQB ,DQPB E DQB ,DQPB DQPB BYTE BYTE BWB DQPC WRITE DRIVER WRITE REGISTER DQPD DQA ,DQPA DQA ,DQPA BYTE BWA BYTE WRITE DRIVER WRITE
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CY7C1360C CY7C1362C Pin Configurations 100-Pin TQFP Pinout (3 Chip Enables) (A Version) DQP C 1 80 DQPB NC A 1 80 DQC 2 79 DQB NC NC 2 79 DQc DQB 3 78 NC NC 3 78 V DDQ V 4 77 V DDQ DDQ 4 77 V DDQ V SSQ V 5 76 V SSQ SSQ 5 76 V SSQ DQC DQB 6 75 NC 6 75 NC DQC DQB 7 74 NC 7 74 DQPA DQC 8 73 DQB DQB DQA 8 73 DQC 9 72 DQB DQB DQA 9 72 V SSQ 10 71 V SSQ V SSQ V 10 71 SSQ V DDQ 11 70 V DDQ V DDQ V 11 70 DDQ DQC 12 69 DQB DQB DQA 12 69 DQC DQB 13 68 DQB DQA 13 68 NC V 14 67 NC SS 14 67 V SS V DD 15 6
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CY7C1360C CY7C1362C Pin Configurations (continued) 100-Pin TQFP Pinout (2 Chip Enables) (AJ Version) DQPC DQPB 1 80 NC 1 80 A DQC 2 79 DQB NC 2 79 NC DQC 3 78 DQB NC NC 3 78 V DDQ 4 77 V DDQ V DDQ V 4 77 DDQ V SSQ 5 76 V SSQ V SSQ V 5 76 SSQ DQC 6 75 DQB NC NC 6 75 DQC DQB 7 74 NC DQPA 7 74 DQC DQB 8 73 DQB 8 73 DQA DQC DQB 9 72 DQB 9 72 DQA V V SSQ 10 71 V SSQ SSQ 10 71 V SSQ V DDQ 11 70 V DDQ V DDQ 11 70 V DDQ DQC 12 69 DQB DQB DQA 12 69 DQC 13 68 DQB DQB DQA 13 68 NC 14 67 V SS NC V 14 67
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CY7C1360C CY7C1362C Pin Configurations (continued) 119-Ball BGA Pinout (2 Chip Enables with JTAG) CY7C1360C (256K x 36) 1 23 4 5 6 7 A V AA A A V ADSP DDQ DDQ B NC/288M CE A ADSC A A NC/576M 2 C NC/144M A A V A A NC/1G DD D DQ DQP V NC V DQP DQ C C SS SS B B E DQ DQ V CE V DQ DQ C C SS 1 SS B B F V DQ V V DQ V DDQ C SS OE SS B DDQ G DQ DQ BW BW DQ DQ ADV C C C B B B H DQ DQ V V DQ DQ GW C C SS SS B B J V V NC V NC V V DDQ DD DD DD DDQ K DQ DQ V CLK V DQ DQ D D SS SS A A L DQ DQ BW NC BW DQ DQ
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CY7C1360C CY7C1362C Pin Configurations (continued) 165-Ball FBGA Pinout (3 Chip Enable with JTAG) CY7C1360C (256K x 36) 1 234 5 6 7 89 10 11 NC/288M A NC A A CE BW BW CE ADSC BWE ADV 1 C B 3 NC/144M A CE2 BW BW CLK A NC/576M B GW OE ADSP D A C DQP NC V V V V V V V NC/1G DQP C DDQ SS SS SS SS SS DDQ B DQ DQ V V V V V V V DQ DQ D C C DDQ DD SS SS SS DD DDQ B B DQ DQ V V V V V V V DQ DQ E C C DDQ DD SS SS SS DD DDQ B B F DQ DQ V V V V V V V DQ DQ C C DDQ DD SS SS SS DD DDQ B B G DQ DQ V V V V V
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CY7C1360C CY7C1362C Pin Definitions Name I/O Description A , A , A Input- Address Inputs used to select one of the address locations. Sampled at the rising edge of 0 1 [2] Synchronous the CLK if ADSP or ADSC is active LOW, and CE , CE , and CE are sampled active. A , A 1 2 3 1 0 are fed to the two-bit counter. . BW , BW Input- Byte Write Select Inputs, active LOW. Qualified with BWE to conduct Byte Writes to the A B BW , BW Synchronous SRAM. Sampled on the rising edge of CLK. C D GW Input-
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CY7C1360C CY7C1362C Pin Definitions (continued) Name I/O Description TDI JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is Synchronous not being utilized, this pin can be disconnected or connected to V . This pin is not available DD on TQFP packages. TMS JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is Synchronous not being utilized, this pin can be disconnected or c
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CY7C1360C CY7C1362C conducted, the data presented to the DQs is written into the clock cycles are required to enter into or exit from this “sleep” corresponding address location in the memory core. If a Byte mode. While in this mode, data integrity is guaranteed. Write is conducted, only the selected bytes are written. Bytes Accesses pending when entering the “sleep” mode are not not selected during a Byte Write operation will remain considered valid nor is the completion of the operation unal
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CY7C1360C CY7C1362C [3, 4, 5, 6, 7, 8] Truth Table (continued) Address Operation Used CE CE CE ZZ ADSP ADSC ADV WRITE OE CLK DQ 1 2 3 READ Cycle, Begin Burst External L H L L H L X H L L-H Q READ Cycle, Begin Burst External L H L L H L X H H L-H Tri-State READ Cycle, Continue Burst Next X X X L H H L H L L-H Q READ Cycle, Continue Burst Next X X X L H H L H H L-H Tri-State READ Cycle, Continue Burst Next H X X L X H L H L L-H Q READ Cycle, Continue Burst Next H X X L X H L H H L-H Tri-State W
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CY7C1360C CY7C1362C [5, 9] Truth Table for Read/Write Function (CY7C1362C) GW BWE BW BW B A Read H H X X Read H L H H Write Byte A – (DQ and DQP)HLHL A A Write Byte B – (DQ and DQP)HLLH B B Write Bytes B, A H L L L Write All Bytes H L L L Write All Bytes L X X X Test Access Port (TAP) IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1360C/CY7C1362C incorporates a serial boundary Test Clock (TCK) scan test access port (TAP) in the BGA package only. The The test clock is used only with the TAP co
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CY7C1360C CY7C1362C Boundary Scan Register TAP Controller Block Diagram 0 The boundary scan register is connected to all the input and Bypass Register bidirectional balls on the SRAM. The boundary scan register is loaded with the contents of the 2 1 0 RAM I/O ring when the TAP controller is in the Capture-DR Selection Instruction Register state and is then placed between the TDI and TDO balls when Selection TDI Circuitry TDO the controller is moved to the Shift-DR state. The EXTEST, C
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CY7C1360C CY7C1362C IDCODE To guarantee that the boundary scan register will capture the correct value of a signal, the SRAM signal must be stabilized The IDCODE instruction causes a vendor-specific, 32-bit code long enough to meet the TAP controller's capture set-up plus to be loaded into the instruction register. It also places the hold times (t and t ). The SRAM clock input might not be CS CH instruction register between the TDI and TDO balls and allows captured correctly if there is no way
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CY7C1360C CY7C1362C [10, 11] TAP AC Switching Characteristics Over the Operating Range Parameter Description Min. Max. Unit Clock t TCK Clock Cycle Time 50 ns TCYC t TCK Clock Frequency 20 MHz TF t TCK Clock HIGH time 20 ns TH t TCK Clock LOW time 20 ns TL Output Times t TCK Clock LOW to TDO Valid 10 ns TDOV t TCK Clock LOW to TDO Invalid 0 ns TDOX Set-up Times t TMS Set-up to TCK Clock Rise 5 ns TMSS t TDI Set-up to TCK Clock Rise 5 ns TDIS t Capture Set-up to TCK Rise 5 ns CS Hold Times t TM
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CY7C1360C CY7C1362C TAP DC Electrical Characteristics And Operating Conditions [12] (0°C < T < +70°C; V = 3.3V ±0.165V unless otherwise noted) (continued) A DD Parameter Description Conditions Min. Max. Unit V Output LOW Voltage I = 100 µA V = 3.3V 0.2 V OL2 OL DDQ V = 2.5V 0.2 V DDQ V Input HIGH Voltage V = 3.3V 2.0 V + 0.3 V IH DDQ DD V = 2.5V 1.7 V + 0.3 V DDQ DD V Input LOW Voltage V = 3.3V –0.5 0.7 V IL DDQ V = 2.5V –0.3 0.7 V DDQ I Input Load Current GND < V < V –5 5 µA X IN DDQ Identifi
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CY7C1360C CY7C1362C 165-ball FBGA Boundary Scan Order CY7C1360C (256K x 36) CY7C1362C (512K x 18) Signal Signal Signal Signal Bit# ball ID Name Bit# ball ID Name Bit# ball ID Name Bit# ball ID Name 1 B6 CLK 37 R6 A0 1 B6 CLK 37 R6 A0 2B7 GW 38 P6 A1 2 B7 GW 38 P6 A1 3A7 BWE 39 R4 A 3 A7 BWE 39 R4 A 4B8 OE 40 P4 A 4 B8 OE 40 P4 A 5A8 ADSC 41 R3 A 5 A8 ADSC 41 R3 A 6B9 ADSP 42 P3 A 6 B9 ADSP 42 P3 A 7A9 ADV 43 R1 MODE 7 A9 ADV 43 R1 MODE 8B10 A 44 N1 DQP 8 B10 A 44 Internal Internal D 9A10 A 4
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CY7C1360C CY7C1362C 119-ball BGA Boundary Scan Order CY7C1360C (256K x 36) CY7C1362C (512K x 18) Signal Signal Signal Signal Bit# ball ID Name Bit# ball ID Name Bit# ball ID Name Bit# ball ID Name 1 CLK 37 P4 A0 1 CLK 37 P4 A0 K4 K4 2H4 GW 38 N4 A1 2 H4 GW 38 N4 A1 3M4 BWE 39 R6 A 3 M4 BWE 39 R6 A 4F4 OE 40 T5 A 4 F4 OE 40 T5 A 5B4 ADSC 41 T3 A 5 B4 ADSC 41 T3 A 6A4 ADSP 42 R2 A 6 A4 ADSP 42 R2 A 7G4 ADV 43 R3 MODE 7 G4 ADV 43 R3 MODE 8C3 A 44 P2 DQP 8 C3 A 44 Internal Internal D 9B3 A 45 P1
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CY7C1360C CY7C1362C DC Input Voltage .................................. –0.5V to VDD + 0.5V Maximum Ratings Current into Outputs (LOW)......................................... 20 mA (Above which the useful life may be impaired. For user guide- Static Discharge Voltage.......................................... > 2001V lines, not tested.) (per MIL-STD-883, Method 3015) Storage Temperature .................................–65°C to +150°C Latch-up Current...........................................
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CY7C1360C CY7C1362C [16] Capacitance 100 TQFP 119 BGA 165 FBGA Parameter Description Test Conditions Max. Max. Max. Unit C Input Capacitance T = 25°C, f = 1 MHz, 55 5 pF IN A V = 3.3V DD C Clock Input Capacitance 5 5 5 pF CLK V = 2.5V DDQ C Input/Output Capacitance 5 7 7 pF I/O [16] Thermal Resistance 100 TQFP 119 BGA 165 FBGA Parameter Description Test Conditions Package Package Package Unit Θ Thermal Resistance Test conditions follow standard test 29.41 34.1 16.8 °C/W JA (Junction to Ambie
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CY7C1360C CY7C1362C [17, 18] Switching Characteristics Over the Operating Range –250 –200 –166 Parameter Description Min. Max. Min. Max. Min. Max. Unit [19] t V (Typical) to the First Access 11 1 ms POWER DD Clock t Clock Cycle Time 4.0 5.0 6.0 ns CYC t Clock HIGH 1.8 2.0 2.4 ns CH t Clock LOW 1.8 2.0 2.4 ns CL Output Times t Data Output Valid after CLK Rise 2.8 3.0 3.5 ns CO t Data Output Hold after CLK Rise 1.25 1.25 1.25 ns DOH [20, 21, 22] t Clock to Low-Z 1.25 1.25 1.25 ns CLZ [20, 21, 2
