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CY7C1146V18, CY7C1157V18
CY7C1148V18, CY7C1150V18
18-Mbit DDR-II+ SRAM 2-Word Burst
Architecture (2.0 Cycle Read Latency)
Features Functional Description
■ 18 Mbit density (2M x 8, 2M x 9, 1M x 18, 512K x 36) The CY7C1146V18, CY7C1157V18, CY7C1148V18, and
CY7C1150V18 are 1.8V Synchronous Pipelined SRAMs
■ 300 MHz to 375 MHz clock for high bandwidth
equipped with DDR-II+ architecture. The DDR-II+ consists of an
SRAM core with advanced synchronous peripheral circuitry.
■ 2-Word burst for reducing
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1M x 8 Array 1M x 9 Array 1M x 8 Array 1M x 9 Array CY7C1146V18, CY7C1157V18 CY7C1148V18, CY7C1150V18 Logic Block Diagram (CY7C1146V18) Write Write 20 A (19:0) Reg Reg Address Register LD 8 K Output CLK K Logic R/W Gen. Control DOFF Read Data Reg. 16 CQ V 8 REF 8 Reg. Reg. CQ Control R/W 8 Logic DQ [7:0] 8 NWS [1:0] Reg. 8 QVLD Logic Block Diagram (CY7C1157V18) Write Write 20 A (19:0) Reg Reg Address Register LD 9 K Output CLK K Logic R/W Gen. Control DOFF Read Data Reg. 18 CQ V 9 REF 9 Reg. Reg
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256K x 36 Array 512K x 18 Array 256K x 36 Array 512K x 18 Array CY7C1146V18, CY7C1157V18 CY7C1148V18, CY7C1150V18 Logic Block Diagram (CY7C1148V18) Write Write 19 A (18:0) Reg Reg Address Register LD 18 K Output CLK K Logic R/W Gen. Control DOFF Read Data Reg. 36 CQ V 18 REF 18 Reg. Reg. CQ Control R/W Logic DQ [17:0] 18 BWS 18 [1:0] Reg. 18 QVLD Logic Block Diagram (CY7C1150V18) Write Write 18 A Reg Reg (17:0) Address Register LD 36 K Output CLK K Logic R/W Gen. Control DOFF Read Data Reg. 72 C
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CY7C1146V18, CY7C1157V18 CY7C1148V18, CY7C1150V18 Pin Configurations 165-Ball FBGA (13 x 15 x 1.4 mm) Pinout CY7C1146V18 (2M x 8) 1 2 3 4 567 89 10 11 NC/72M A NC/144M A NC/36M CQ A CQ R/W NWS K LD 1 NC NC NC A NC/288M K A NC NC DQ3 B NWS 0 C NC NC NC V AAA V NC NC NC SS SS NC NC V V V V NC NC D NC V NC SS SS SS SS SS NC NC V V V V NC DQ2 E DQ4 V NC DDQ SS SS SS DDQ F NC NC NC V V V V V NC NC NC DDQ DD SS DD DDQ G NC NC DQ5 V V V V V NC NC NC DDQ DD SS DD DDQ H V V V V V V V V V ZQ REF DDQ DDQ
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CY7C1146V18, CY7C1157V18 CY7C1148V18, CY7C1150V18 Pin Configurations (continued) 165-Ball FBGA (13 x 15 x 1.4 mm) Pinout CY7C1148V18 (1M x 18) 1 2 3 4 567 89 10 11 NC/72M A NC/144M A NC/36M CQ A K CQ R/W BWS LD 1 NC DQ9 NC A NC/288M K A NC NC DQ8 B BWS 0 C NC NC NC V ANC A V NC DQ7 NC SS SS NC NC V V V V NC NC D DQ10 V NC SS SS SS SS SS NC NC V V V V NC DQ6 E DQ11 V NC DDQ SS SS SS DDQ F NC DQ12 NC V V V V V NC NC DQ5 DDQ DD SS DD DDQ G NC NC DQ13 V V V V V NC NC NC DDQ DD SS DD DDQ V V V V V V
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CY7C1146V18, CY7C1157V18 CY7C1148V18, CY7C1150V18 Pin Definitions Pin Name IO Pin Description DQ Input Output- Data Input Output Signals. Inputs are sampled on the rising edge of K and K clocks when write [x:0] Synchronous operations are valid. These pins drive out the requested data when a read operation is active. Valid data is driven out on the rising edge of both the K and K clocks when read operations are active. When read access is deselected, Q are automatically tri-stated. [x:0] CY7C1
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CY7C1146V18, CY7C1157V18 CY7C1148V18, CY7C1150V18 Pin Definitions (continued) Pin Name IO Pin Description DOFF Input DLL Turn Off − Active LOW. Connecting this pin to ground turns off the DLL inside the device. The timings in the DLL turned off operation are different from those listed in this data sheet. For normal operation, connect this pin to a pull up through a 10 KΩ or less pull up resistor. The device behaves in DDR-I mode when the DLL is turned off. In this mode, operate the device at
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CY7C1146V18, CY7C1157V18 CY7C1148V18, CY7C1150V18 Byte Write Operations Functional Overview Byte Write operations are supported by the CY7C1148V18. A The CY7C1146V18, CY7C1157V18, CY7C1148V18, and write operation is initiated as described in the Write Operations. CY7C1150V18 are synchronous pipelined Burst SRAMs The bytes that are written are determined by BWS and BWS 0 1 equipped with a DDR interface. which are sampled with each set of 18-bit data word. Asserting Accesses are initiated on the
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CY7C1146V18, CY7C1157V18 CY7C1148V18, CY7C1150V18 echo clock and follows the timing of any data pin. This signal is DDR-I mode (with 1.0 cycle latency and a longer access time). asserted half a cycle before valid data arrives. For more information, refer to the application note, “DLL Consid- erations in QDRII/DDRII/QDRII+/DDRII+”. The DLL can also be DLL reset by slowing or stopping the input clocks K and K for a minimum of 30 ns. However, it is not necessary for the DLL to be These chips utiliz
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CY7C1146V18, CY7C1157V18 CY7C1148V18, CY7C1150V18 Write Cycle Descriptions [3, 9] The write cycle descriptions of CY7C1146V18 and CY7C1148V18 follows. BWS / BWS / 0 1 K Comments K NWS NWS 0 1 L L L – H – When the Data portion of a write sequence is active: CY7C1146V18 − both nibbles (D ) are written into the device. [7:0] CY7C1148V18 − both bytes (D ) are written into the device. [17:0] L L – L – H When the Data portion of a write sequence is active: CY7C1146V18 − both nibbles (D ) are writte
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CY7C1146V18, CY7C1157V18 CY7C1148V18, CY7C1150V18 [3, 9] The write cycle descriptions of CY7C1148V18 follows, BWS BWS BWS BWS K K Comments 0 1 2 3 LLLL L – H – When the Data portion of a write sequence is active, all four bytes (D ) are [35:0] written into the device. LLLL – L – H When the Data portion of a write sequence is active, all four bytes (D ) are [35:0] written into the device. L H H H L – H – When the Data portion of a write sequence is active, only the lower byte (D ) is [8:0]
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CY7C1146V18, CY7C1157V18 CY7C1148V18, CY7C1150V18 Instruction Register IEEE 1149.1 Serial Boundary Scan (JTAG) Serially load three-bit instructions into the instruction register. These SRAMs incorporate a serial boundary scan test access This register is loaded when it is placed between the TDI and port (TAP) in the FBGA package. This part is fully compliant with TDO pins as shown in “TAP Controller Block Diagram” on IEEE Standard 1149.1-2001. The TAP operates using JEDEC page 15. Upon power up,
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CY7C1146V18, CY7C1157V18 CY7C1148V18, CY7C1150V18 IDCODE PRELOAD enables an initial data pattern to be placed at the latched parallel outputs of the boundary scan register cells be- The IDCODE instruction causes a vendor-specific, 32-bit code fore the selection of another boundary scan test operation. to be loaded into the instruction register. It also places the instruction register between the TDI and TDO pins and enables The shifting of data for the SAMPLE and PRELOAD phases can the IDCODE to
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CY7C1146V18, CY7C1157V18 CY7C1148V18, CY7C1150V18 TAP Controller State Diagram [10] Figure 2 shows the tap controller state diagram. Figure 2. Tap Controller State Diagram TEST-LOGIC 1 RESET 0 1 1 1 TEST-LOGIC/ SELECT SELECT 0 IDLE DR-SCAN IR-SCAN 0 0 1 1 CAPTURE-DR CAPTURE-IR 0 0 SHIFT-DR 0 SHIFT-IR 0 1 1 1 1 EXIT1-DR EXIT1-IR 0 0 0 0 PAUSE-DR PAUSE-IR 1 1 0 0 EXIT2-DR EXIT2-IR 1 1 UPDATE-DR UPDATE-IR 1 1 0 0 Note 10. The 0/1 next to each state represents the value at TMS at the rising edge of
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CY7C1146V18, CY7C1157V18 CY7C1148V18, CY7C1150V18 TAP Controller Block Diagram Figure 3. Tap Controller Block Diagram 0 Bypass Register Selection Selection TDI 2 1 0 TDO Circuitry Circuitry Instruction Register 29 31 30 . . 2 1 0 Identification Register 106 . . . . 2 1 0 Boundary Scan Register TCK TAP Controller TMS TAP Electrical Characteristics [11, 12, 13] The Tap Electrical Characteristics table over the operating range follows. Parameter Description Test Conditions Min Max Unit V Output HI
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CY7C1146V18, CY7C1157V18 CY7C1148V18, CY7C1150V18 TAP AC Switching Characteristics [14, 15] The Tap AC Switching Characteristics table over the operating range follows. Parameter Description Min Max Unit t TCK Clock Cycle Time 50 ns TCYC t TCK Clock Frequency 20 MHz TF t TCK Clock HIGH 20 ns TH t TCK Clock LOW 20 ns TL Setup Times t TMS Setup to TCK Clock Rise 5 ns TMSS t TDI Setup to TCK Clock Rise 5 ns TDIS t Capture Setup to TCK Rise 5 ns CS Hold Times t TMS Hold after TCK Clock Rise 5 ns TM
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CY7C1146V18, CY7C1157V18 CY7C1148V18, CY7C1150V18 Identification Register Definitions Value Instruction Field Description CY7C1146V18 CY7C1157V18 CY7C1148V18 CY7C1150V18 Revision Number 000 000 000 000 Version number. (31:29) Cypress Device ID 11010111100000101 11010111100001101 11010111100010101 11010111100100101 Defines the type of (28:12) SRAM. Cypress JEDEC ID 00000110100 00000110100 00000110100 00000110100 Allows unique (11:1) identification of SRAM vendor. ID Register 1 1 1 1 Indicates
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CY7C1146V18, CY7C1157V18 CY7C1148V18, CY7C1150V18 Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID 0 6R 27 11H 54 7B 81 3G 1 6P 28 10G 55 6B 82 2G 26N 29 9G 56 6A 83 1J 3 7P 30 11F 57 5B 84 2J 4 7N 31 11G 58 5A 85 3K 57R 32 9F 59 4A 86 3J 6 8R 33 10F 60 5C 87 2K 7 8P 34 11E 61 4B 88 1K 8 9R 35 10E 62 3A 89 2L 9 11P 36 10D 63 1H 90 3L 10 10P 37 9E 64 1A 91 1M 11 10N 38 10C 65 2B 92 1L 12 9P 39 11D 66 3B 93 3N 13 10M 40 9C 67 1C 94 3M 14 11N 419D 68 1B 951N 15 9M 42 11B
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CY7C1146V18, CY7C1157V18 CY7C1148V18, CY7C1150V18 Power Up Sequence in DDR-II+ SRAM DLL Constraints During Power Up, when the DOFF is tied HIGH, the DLL gets ■ DLL uses K clock as its synchronizing input. The input must locked after 2048 cycles of stable clock. DDR-II+ SRAMs must have low phase jitter, which is specified as t . KC Var be powered up and initialized in a predefined manner to prevent ■ The DLL functions at frequencies down to 120 MHz. undefined operations. ■ If the input clock is
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CY7C1146V18, CY7C1157V18 CY7C1148V18, CY7C1150V18 Current into Outputs (LOW)......................................... 20 mA Maximum Ratings Static Discharge Voltage (MIL-STD-883, M 3015).... >2001V Exceeding maximum ratings may shorten the useful life of the Latch up Current..................................................... >200 mA device. These user guidelines are not tested. Storage Temperature ................................ –65°C to + 150°C Operating Range Ambient Temperature with Power
