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®
CY62157ESL MoBL
8-Mbit (512K x 16) Static RAM
into standby mode when deselected (CE HIGH or both BHE and
Features
BLE are HIGH). The input or output pins (IO through IO ) are
0 15
placed in a high impedance state when:
■ Very high speed: 45 ns
■ Deselected (CE HIGH)
■ Wide voltage range: 2.2V–3.6V and 4.5V–5.5V
■ Ultra low standby power ■ Outputs are disabled (OE HIGH)
❐ Typical Standby current: 2 μA
■ Both Byte High Enable and Byte Low Enable are disabled
❐ Maximum Standby current: 8 μA
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® CY62157ESL MoBL Pin Configuration Figure 1. 44-Pin TSOP II (Top View) A A 1 44 5 4 A A 2 43 3 6 A A 3 42 7 2 A 4 OE 41 1 A 5 0 40 BHE 6 39 CE BLE IO 7 38 IO 0 15 IO 8 37 IO 1 14 IO 9 IO 2 36 13 IO 10 35 IO 3 12 V V 11 34 CC SS V SS 12 33 V CC IO 4 13 32 IO 11 IO IO 5 14 31 10 IO IO 15 30 6 9 IO 16 29 IO 7 8 A 17 28 WE 8 A 18 27 A 18 9 A A 19 26 17 10 A 20 25 A 16 11 A 21 24 A 15 12 A A 22 23 14 13 Product Portfolio Power Dissipation Operating I , (mA) CC [1] Speed Standby, I SB2 Product Ran
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® CY62157ESL MoBL Output Current into Outputs (LOW)............................. 20 mA Maximum Ratings Static Discharge Voltage............................................ >2001V Exceeding the maximum ratings may impair the useful life of the (MIL-STD-883, Method 3015) device. These user guidelines are not tested. Latch up Current...................................................... >200 mA Storage Temperature.................................. –65°C to +150°C Operating Range Ambient Temperature
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® CY62157ESL MoBL Capacitance Tested initially and after any design or process changes that may affect these parameters. Parameter Description Test Conditions Max Unit C Input Capacitance T = 25°C, f = 1 MHz, V = V 10 pF IN A CC CC(typ) Output Capacitance 10 pF C OUT Thermal Resistance Tested initially and after any design or process changes that may affect these parameters. Parameter Description Test Conditions TSOP II Unit Thermal Resistance Still Air, soldered on a 3 × 4.5 inch, two-layer 77
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® CY62157ESL MoBL Data Retention Characteristics Over the Operating Range [2] Parameter Description Conditions Min Typ Max Unit V V for Data Retention 1.5 V DR CC I Data Retention Current CE > V – 0.2V, V = 1.5V 2 5 μA CC CC CCDR V > V – 0.2V or V < 0.2V IN CC IN = 2.0V 2 8 V CC [6] t Chip Deselect to Data 0ns CDR Retention Time [7] t Operation Recovery Time t ns R RC Data Retention Waveform DATA RETENTION MODE V V CC(min) V > 1.5V CC(min) V DR CC t t CDR R CE or [8] BHE.BLE Notes 6. Tested i
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® CY62157ESL MoBL Switching Characteristics [9] Over the Operating Range 45 ns Parameter Description Unit Min Max Read Cycle t Read Cycle Time 45 ns RC t Address to Data Valid 45 ns AA t Data Hold from Address Change 10 ns OHA t CE LOW to Data Valid 45 ns ACE t OE LOW to Data Valid 22 ns DOE [10] t OE LOW to LOW-Z 5ns LZOE [10, 11] t OE HIGH to High-Z 18 ns HZOE [10] t CE LOW to Low-Z 10 ns LZCE [10, 11] t CE HIGH to High-Z 18 ns HZCE t CE LOW to Power Up 0 ns PU t CE HIGH to Power Down 45 ns
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® CY62157ESL MoBL Switching Waveforms [14, 15] Figure 2. Read Cycle No.1: Address Transition Controlled. t RC RC ADDRESS t AA t OHA DATA OUT PREVIOUS DATA VALID DATA VALID [15, 16] Figure 3. Read Cycle No. 2: OE Controlled ADDRESS t RC CE t PD t t HZCE ACE OE t HZOE t DOE t LZOE BHE/BLE t HZBE t DBE t LZBE HIGH IMPEDANCE HIGHI MPEDANCE DATA VALID DATA OUT t LZCE t PU I CC V 50% CC 50% I SUPPLY SB CURRENT Notes 14. The device is continuously selected. OE, CE = V , BHE, BLE, or both = V . IL
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® CY62157ESL MoBL Switching Waveforms (continued) [13, 17, 18] Figure 4. Write Cycle No 1: WE Controlled t WC ADDRESS t SCE CE t t AW HA t t SA PWE WE t BW BHE/BLE OE t HD t SD NOTE 19 DATA IN DATA IO t HZOE [13, 17, 18] Figure 5. Write Cycle 2: CE Controlled t WC ADDRESS t SCE CE t SA t t AW HA t PWE WE t BW BHE/BLE OE t t SD HD DATA DATA IO NOTE 19 IN t HZOE Notes 17. Data IO is high impedance if OE = V . IH 18. If CE goes HIGH simultaneously with WE = V , the output remains in a high impe
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® CY62157ESL MoBL Switching Waveforms (continued) [18] Figure 6. Write Cycle 3: WE controlled, OE LOW t WC ADDRESS t SCE CE t BW BHE/BLE t t AW HA t t SA PWE WE t HD t SD DATA IO NOTE 19 DATA IN t LZWE t HZWE [18] Figure 7. Write Cycle 4: BHE/BLE Controlled, OE LOW t WC ADDRESS CE t SCE t t AW HA t BW BHE/BLE t SA t PWE WE t HZWE t HD t SD NOTE 19 DATA DATA IO IN t LZWE Document #: 001-43141 Rev. ** Page 9 of 12 [+] Feedback [+] Feedback
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® CY62157ESL MoBL Truth Table CE WE OE BHE BLE Inputs/Outputs Mode Power H X X X X High-Z Deselect/Power down Standby (I ) SB X X X H H High-Z Deselect/Power down Standby (I ) SB L H L L L Data Out (IO –IO )Read Active (I ) 0 15 CC LH LHL Data Out (IO –IO ); Read Active (I ) 0 7 CC IO –IO in High-Z 8 15 L H L L H Data Out (IO –IO ); ) Read Active (I 8 15 CC IO –IO in High-Z 0 7 L H H L L High-Z Output Disabled Active (I ) CC L H H H L High-Z Output Disabled Active (I ) CC L H H L H High-Z Outp
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® CY62157ESL MoBL Package Diagrams Figure 8. 44-Pin TSOP II, 51-85087 51-85087-*A Document #: 001-43141 Rev. ** Page 11 of 12 [+] Feedback [+] Feedback
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® CY62157ESL MoBL Document History Page ® Document Title: CY62157ESL MoBL 8-Mbit (512K x 16) Static RAM Document Number: 001-43141 Orig. of REV. ECN NO. Issue Date Change Description of Change ** 1875228 See ECN VKN/AESA New Data Sheet © Cypress Semiconductor Corporation, 2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does
