Resumen del contenido incluido en la página 1
CY14B101Q1
CY14B101Q2
PRELIMINARY
CY14B101Q3
1 Mbit (128K x 8) Serial SPI nvSRAM
■ Low Power Consumption
Features
❐ Single 3V +20%, –10% operation
■ 1 Mbit NonVolatile SRAM
❐ Average Vcc current of 10 mA at 40 MHz operation
❐ Internally organized as 128K x 8
■ Industry Standard Configurations
®
❐ STORE to QuantumTrap nonvolatile elements initiated au-
® ❐ Commercial and industrial temperatures
tomatically on power down (AutoStore ) or by user using
❐ CY14B101Q1 has identical pin configuration
Resumen del contenido incluido en la página 2
CY14B101Q1 CY14B101Q2 PRELIMINARY CY14B101Q3 Pinouts [1, 2, 3] Figure 1. Pin Diagram - 8-Pin DFN CS CS V V CY14B101Q2 CY14B101Q1 CC CC SO SO HOLD HOLD Top View Top View V WP SCK SCK CAP not to scale not to scale GND GND SI SI Figure 2. Pin Diagram - 16-Pin SOIC 16 V NC 1 CC NC 15 2 NC 14 NC 3 V CAP CY14B101Q3 13 NC 4 SO Top View 12 5 WP SI not to scale 6 11 SCK HOLD 10 7 NC CS 9 8 GND HSB Table 1. Pin Definitions Pin Name I/O Type Description CS Input Chip Select. Activates the device when p
Resumen del contenido incluido en la página 3
CY14B101Q1 CY14B101Q2 PRELIMINARY CY14B101Q3 SRAM Write Device Operation All writes to nvSRAM are carried out on the SRAM and do not CY14B101Q1/CY14B101Q2/CY14B101Q3 is 1 Mbit nvSRAM use up any endurance cycles of the nonvolatile memory. This memory with a nonvolatile element in each memory cell. All the enables user to perform infinite write operations. A Write cycle is reads and writes to nvSRAM happen to the SRAM which gives performed through the SPI WRITE instruction. The WRITE nvSRAM the u
Resumen del contenido incluido en la página 4
CY14B101Q1 CY14B101Q2 PRELIMINARY CY14B101Q3 capacitor (V ) and enables the device to safely STORE the Figure 3. AutoStore Mode CAP data in the nonvolatile memory when power goes down. Vcc During normal operation, the device draws current from V to CC charge the capacitor connected to the V pin. When the CAP 0.1uF voltage on the V pin drops below V during power down, CC SWITCH the device inhibits all memory accesses to nvSRAM and automatically performs a conditional STORE operation using the
Resumen del contenido incluido en la página 5
CY14B101Q1 CY14B101Q2 PRELIMINARY CY14B101Q3 Note CY14B101Q2/CY14B101Q3 has AutoStore Enabled from not selected, data through the SI pin is ignored and the serial the factory. In CY14B101Q1, V pin is not present and output pin (SO) remains in a high impedance state. CAP AutoStore option is not available. The Autostore Enable and Note A new instruction must begin with the falling edge of Chip Disable instructions to CY14B101Q1 are ignored. Select (CS). Therefore, only one opcode can be issued fo
Resumen del contenido incluido en la página 6
CY14B101Q1 CY14B101Q2 PRELIMINARY CY14B101Q3 Figure 4. System Configuration Using SPI nvSRAM SCK MOSI MISO SS C K SI SO CK S I SO uController C Y 1 4B 10 1 Q x C Y 1 4 B 1 0 1Q x CS HOLD CS HOLD CS1 HOLD1 CS2 HOLD2 SPI Modes The two SPI modes are shown in Figure 5 and Figure 6. The status of clock when the bus master is in Standby mode and not CY14B101Q1/CY14B101Q2/CY14B101Q3 may be driven by a transferring data is: microcontroller with its SPI peripheral running in either of the following two
Resumen del contenido incluido en la página 7
CY14B101Q1 CY14B101Q2 PRELIMINARY CY14B101Q3 Active Power and Standby Power Modes SPI Operating Features When Chip Select (CS) is LOW, the device is selected, and is in Power Up the Active Power mode. The device consumes I current, as CC Power up is defined as the condition when the power supply is specified in DC Electrical Characteristics on page 13. When Chip turned on and V crosses Vswitch voltage. During this time, the CC Select (CS) is HIGH, the device is deselected and the device Chip Sel
Resumen del contenido incluido en la página 8
CY14B101Q1 CY14B101Q2 PRELIMINARY CY14B101Q3 RDSR instruction. However, only WPEN, BP1, and BP0 bits of Status Register the Status Register can be modified by using WRSR instruction. The status register bits are listed in Table 3. The status register WRSR instruction has no effect on WEN and RDY bits. The consists of Ready bit (RDY) and data protection bits BP1, BP0, default value shipped from the factory for BP1, BP2 and WPEN WEN, and WPEN. The RDY bit can be polled to check the Ready bits is ‘
Resumen del contenido incluido en la página 9
CY14B101Q1 CY14B101Q2 PRELIMINARY CY14B101Q3 Figure 8. Write Status Register (WRSR) Instruction Timing CS 0 1 2 3 4567 0 12345 67 SCK Data in Opcode SI 1 D7 0 0 0 D3 D2 0 0 0000 0 0 0 MSB LSB HI-Z SO Write Disable (WRDI) Instruction Write Protection and Block Protection Write Disable instruction disables the write by clearing the WEN CY14B101Q1/CY14B101Q2/CY14B101Q3 provides features bit to ‘0’ in order to protect the device against inadvertent writes. for both software and hardware write prote
Resumen del contenido incluido en la página 10
CY14B101Q1 CY14B101Q2 PRELIMINARY CY14B101Q3 Serial Output (SO) pin. The following sequence needs to be Write Protect (WP) Pin followed for a read operation: After the CS line is pulled LOW to The write protect pin (WP) is used to provide hardware write select a device, the read opcode is transmitted through the SI protection. WP pin enables all normal read and write operations line followed by three bytes of address. The Most Significant when held HIGH. When the WP pin is brought LOW and WPEN
Resumen del contenido incluido en la página 11
CY14B101Q1 CY14B101Q2 PRELIMINARY CY14B101Q3 Figure 12. Burst Mode Read Instruction Timing CS 01 2 3 456 7 0 1 2 3 4 5 6 7 20 21 22 23 0123 4 5 67 0 0 1 234 567 7 SCK Op-Code 17-bit Address A16 SI 00 00 00 11 0 0 00 00 0 A3 A2 A1 A0 MSB LSB Data Byte N Data Byte 1 SO D7 D6 D5 D4 D3 D2 D1 D0 D7 D0 D7 D6 D5 D4 D3 D2 D1 D0 MSB LSB MSB LSB Figure 13. Write Instruction Timing CS 0123 4 5 7 0 1 2 3 4 5 6 7 20 21 2223 01234567 6 SCK Op-Code 17-bit Address SI 00 00 001 0 0 0 A16 A3 A2 A1 A0 D7 D6 D5
Resumen del contenido incluido en la página 12
CY14B101Q1 CY14B101Q2 PRELIMINARY CY14B101Q3 bit is cleared on the positive edge of CS following the STORE AutoStore Enable (ASENB) instruction. The AutoStore Enable instruction enables the AutoStore on Figure 15. Software STORE Operation CY14B101Q1. This setting is not nonvolatile and needs to be followed by a STORE sequence to survive the power cycle. CS To issue this instruction, the device must be write enabled (WEN 0 1 2 3 4 5 6 7 = ‘1’). The instruction is performed by transmittin
Resumen del contenido incluido en la página 13
CY14B101Q1 CY14B101Q2 PRELIMINARY CY14B101Q3 Transient Voltage (<20 ns) on Maximum Ratings Any Pin to Ground Potential .................. –2.0V to V + 2.0V CC Exceeding maximum ratings may shorten the useful life of the Package Power Dissipation device. These user guidelines are not tested. Capability (T = 25°C) ................................................... 1.0W A Storage Temperature ................................. –65 °C to +150 °C Surface Mount Lead Soldering Temperature (3 Seconds).
Resumen del contenido incluido en la página 14
CY14B101Q1 CY14B101Q2 PRELIMINARY CY14B101Q3 Data Retention and Endurance Parameter Description Min Unit DATA Data Retention 20 Years R NV Nonvolatile STORE Operations 200 K C Capacitance [6] Description Test Conditions Max Unit Parameter C Input Capacitance T = 25 °C, f = 1MHz, 6pF IN A V = 3.0V CC C Output Pin Capacitance 8 pF OUT Thermal Resistance [6] Description Test Conditions 8-SOIC 8-DFN Unit Parameter Θ Thermal Resistance Test conditions follow standard test TBD TBD °C/W JA (Junction
Resumen del contenido incluido en la página 15
CY14B101Q1 CY14B101Q2 PRELIMINARY CY14B101Q3 AC Switching Characteristics 40MHz Cypress Alt. Description Unit Parameter Parameter Min Max f f Clock Frequency, SCK 40 MHz SCK SCK t t Clock Pulse Width Low 11 ns CL WL t t Clock Pulse Width High 11 ns CH WH t t CS High Time 20 ns CS CE t t CS Setup Time 10 ns CSS CES t t CS Hold Time 10 ns CSH CEH t t Data In Setup Time 5 ns SD SU t t Data In Hold Time 5 ns HD H t t HOLD Hold Time 5 ns HH HD t t HOLD Setup Time 5 ns SH CD t t Output Valid 9 ns CO
Resumen del contenido incluido en la página 16
CY14B101Q1 CY14B101Q2 PRELIMINARY CY14B101Q3 AutoStore or Power Up RECALL CY‘4B101QxA Parameters Description Unit Min Max [7] Power Up RECALL Duration 20 ms t FA [8] STORE Cycle Duration 8ms t STORE [9] Time Allowed to Complete SRAM Cycle 25 ns t DELAY V Low Voltage Trigger Level 2.65 V SWITCH t VCC Rise Time 150 μs VCCRISE [6] HSB Output Driver Disable Voltage 1.9 V V HDIS t HSB To Output Active Time 5 μs LZHSB t HSB High Active Time 500 ns HHHD Switching Waveforms [10] Figure 23. AutoStore
Resumen del contenido incluido en la página 17
CY14B101Q1 CY14B101Q2 PRELIMINARY CY14B101Q3 Software Controlled STORE and RECALL Cycles CY14B101Q1 Parameter Description Unit Min Max t RECALL Duration 200 μs RECALL [12, 13] t Soft Sequence Processing Time 100 μs SS Switching Waveforms [12] Figure 24. Software STORE Cycle CS 0 1 2 3 4 5 6 7 SCK 0 0 1 1 1 1 0 0 SI t STORE Hi-Z RWI RDY [12] Figure 25. Software RECALL Cycle CS 0 1 2 3 4 5 6 7 SCK 0 1 1 0 0 0 0 0 SI t RECALL Hi-Z RWI RDY Notes 12. This is the amount of time it t
Resumen del contenido incluido en la página 18
CY14B101Q1 CY14B101Q2 PRELIMINARY CY14B101Q3 Hardware STORE Cycle CY14B101Q1 Parameter Description Unit Min Max t HSB To Output Active Time when write latch not set 25 ns DHSB t Hardware STORE Pulse Width 15 ns PHSB Switching Waveforms [8] Figure 26. Hardware STORE Cycle Write Latch set t PHSB HSB (IN) t STORE t t HHHD DELAY HSB (OUT) t LZHSB SO RWI Write Latch not set t PHSB HSB (IN) HSB pin is driven high to V only by Internal CC 100K resistor, HSB driver is disabled SRAM is disabled as lo
Resumen del contenido incluido en la página 19
CY14B101Q1 CY14B101Q2 PRELIMINARY CY14B101Q3 Ordering Information Package Operating Ordering Code Package Type Diagram Range CY14B101Q1-LHXIT 001-50671 8 DFN (with WP) Industrial CY14B101Q1-LHXI 001-50671 8 DFN (with WP) CY14B101Q1-LHXCT 001-50671 8 DFN (with WP) Commercial CY14B101Q1-LHXC 001-50671 8 DFN (with WP) CY14B101Q2-LHXIT 001-50671 8 DFN (with V ) Industrial CAP CY14B101Q2-LHXI 001-50671 8 DFN (with V ) CAP CY14B101Q2-LHXCT 001-50671 8 DFN (with V ) Commercial CAP CY14B101Q2-LHXC 001-5
Resumen del contenido incluido en la página 20
CY14B101Q1 CY14B101Q2 PRELIMINARY CY14B101Q3 Package Diagrams Figure 27. 8-Pin (300 mil) DFN Package (001-50671) NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS 2. PACKAGE WEIGHT: TBD 3. BASED ON REF JEDEC # MO-240 EXCEPT DIMENSIONS (L) and (b) 001-50671 *A Document #: 001-50091 Rev. *A Page 20 of 22 [+] Feedback
