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Rev. 1.0, Jul. 2010
M471B1G73AH0
204pin Unbuffered SODIMM
based on 4Gb A-die
78FBGA with Lead-Free & Halogen-Free
(RoHS compliant)
datasheet
SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND
SPECIFICATIONS WITHOUT NOTICE.
Products and specifications discussed herein are for reference purposes only. All information discussed
herein is provided on an "AS IS" basis, without warranties of any kind.
This document and all information discussed herein remain the sole and exc
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Rev. 1.0 Unbuffered SODIMM datasheet DDR3 SDRAM Revision History Revision No. History Draft Date Remark Editor 1.0 - First Release Jul. 2010 - S.H.Kim - 2 -
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Rev. 1.0 Unbuffered SODIMM datasheet DDR3 SDRAM Table Of Contents 204pin Unbuffered SODIMM based on 4Gb A-die 1. DDR3 Unbuffered SODIMM Ordering Information........................................................................................................4 2. Key Features.................................................................................................................................................................4 3. Address Configuration ...................................
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Rev. 1.0 Unbuffered SODIMM datasheet DDR3 SDRAM 1. DDR3 Unbuffered SODIMM Ordering Information Number of 2 Density Organization Component Composition Height Part Number Rank M471B1G73AH0-CF8/H9 8GB 1Gx64 512Mx8(K4B4G0846A-HC##)*16 2 30mm NOTE : 1. "##" - F8/H9 2. F8 - 1066Mbps 7-7-7 & H9 - 1333Mbps 9-9-9 - DDR3-1333(9-9-9) is backward compatible to DDR3-1066(7-7-7) 2. Key Features DDR3-800 DDR3-1066 DDR3-1333 Speed Unit 6-6-6 7-7-7 9-9-9 tCK(min) 2.5 1.875 1.5 ns CAS Latency 6 79 tCK tRCD(mi
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Rev. 1.0 Unbuffered SODIMM datasheet DDR3 SDRAM 4. x64 DIMM Pin Configurations (Front side/Back Side) Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back 1 V 2 V 71 V 72 V 139 V 140 DQ38 REFDQ SS SS SS SS V 141 3 4 DQ4 KEY DQ34 142 DQ39 SS 143 V 5 DQ0 6 DQ5 73 CKE0 74 CKE1 DQ35 144 SS V V V 145 V 7DQ1 8 75 76 146 DQ44 SS DD DD SS 3 V 147 9 10 DQS077 NC 78 DQ40 148 DQ45 SS A15 3 149 V 11 DM0 12DQS079 BA2 80 DQ41 150 A14 SS 13 V 14 V 81 V 82 V 151 V 152 DQS5 SS SS DD DD SS 15 DQ2 16 DQ6 83 A1
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Rev. 1.0 Unbuffered SODIMM datasheet DDR3 SDRAM 5. Pin Description Pin Name Description Number Pin Name Description Number CK0, CK1 Clock Inputs, positive line 2 DQ0-DQ63 Data Input/Output 64 Data Masks/ Data strobes, CK0, CK1 Clock Inputs, negative line 2 DM0-DM7 8 Termination data strobes CKE0, CKE1 Clock Enables 2 DQS0-DQS7 Data strobes 8 RAS Row Address Strobe 1 DQS0-DQS7 Data strobes complement 8 CAS Column Address Strobe 1 RESET Reset Pin 1 Logic Analyzer specific test pin (No connect WE
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Rev. 1.0 Unbuffered SODIMM datasheet DDR3 SDRAM 6. Input/Output Functional Description Symbol Type Function The system clock inputs. All address and command lines are sampled on the cross point of the rising edge of CK and CK0-CK1 Input falling edge of CK. A Delay Locked Loop (DLL) circuit is driven from the clock inputs and output timing for read opera- CK0-CK1 tions is synchronized to the input clock. Activates the DDR3 SDRAM CK signal when high and deactivates the CK signal when low. By deac
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Rev. 1.0 Unbuffered SODIMM datasheet DDR3 SDRAM 7. Function Block Diagram: 7.1 8GB, 1Gx64 Module (Populated as 2 ranks of x8 DDR3 SDRAMs) V V DD DD Vtt Vtt Vtt 240Ω 240Ω 240Ω 240Ω DQS3 DQS4 DQS DQS DQS DQS ± 1% ± 1% ± 1% ± 1% DQS3 DQS4 DQS DQS DQS DQS ZQ ZQ ZQ ZQ DM3 DM DM DM DM DM4 DQ[24:31] DQ[0:7] DQ[0:7] DQ[0:7] DQ[0:7] DQ[32:39] D11 D3 D4 D12 240Ω 240Ω 240Ω 240Ω DQS1 DQS DQS DQS DQS DQS6 ± 1% ± 1% ± 1% ± 1% DQS1 DQS DQS DQS DQS DQS6 ZQ ZQ ZQ ZQ DM1 DM DM DM DM DM6 DQ[0:7] DQ[0:7] DQ[0:7] DQ
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Rev. 1.0 Unbuffered SODIMM datasheet DDR3 SDRAM 8. Absolute Maximum Ratings 8.1 Absolute Maximum DC Ratings Symbol Parameter Rating Units NOTE V Voltage on V pin relative to V -0.4 V ~ 1.975 V V 1,3 DD DD SS V Voltage on V pin relative to V -0.4 V ~ 1.975 V V 1,3 DDQ DDQ SS V V Voltage on any pin relative to V -0.4 V ~ 1.975 V V 1 IN, OUT SS T Storage Temperature -55 to +100 °C 1, 2 STG NOTE : 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to t
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Rev. 1.0 Unbuffered SODIMM datasheet DDR3 SDRAM 10. AC & DC Input Measurement Levels 10.1 AC & DC Logic Input Levels for Single-ended Signals [ Table 1 ] Single-ended AC & DC input levels for Command and Address DDR3-800/1066/1333/1600 Symbol Parameter Unit NOTE Min. Max. V (DC100) V + 100 V DC input logic high mV 1,5 IH.CA REF DD V (DC100) V V - 100 DC input logic low mV 1,6 IL.CA SS REF V (AC175) V + 175 AC input logic high - mV 1,2,7 IH.CA REF V (AC175) V - 175 AC input logic low - mV 1,2,8 I
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Rev. 1.0 Unbuffered SODIMM datasheet DDR3 SDRAM 10.2 V Tolerances. REF The dc-tolerance limits and ac-noise limits for the reference voltages V and V are illustrate in Figure 1. It shows a valid reference voltage REFCA REFDQ V (t) as a function of time. (V stands for V and V likewise). REF REF REFCA REFDQ V (DC) is the linear average of V (t) over a very long period of time (e.g. 1 sec). This average has to meet the min/max requirements of V . Fur- REF REF REF thermore V (t) may temporarily d
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Rev. 1.0 Unbuffered SODIMM datasheet DDR3 SDRAM 10.3 AC and DC Logic Input Levels for Differential Signals 10.3.1 Differential Signals Definition tDVAC V .DIFF.AC.MIN IH V .DIFF.MIN IH 0.0 half cycle V .DIFF.MAX IL V .DIFF.AC.MAX IL tDVAC time Figure 2. Definition of differential ac-swing and "time above ac level" tDVAC 10.3.2 Differential Swing Requirement for Clock (CK-CK) and Strobe (DQS-DQS) DDR3-800/1066/1333/1600 Symbol Parameter unit NOTE min max V differential input high +0.2 NOTE 3 V 1
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Rev. 1.0 Unbuffered SODIMM datasheet DDR3 SDRAM 10.3.3 Single-ended Requirements for Differential Signals Each individual component of a differential signal (CK, DQS, CK, DQS) has also to comply with certain requirements for single-ended signals. CK and CK have to approximately reach V min / V max (approximately equal to the ac-levels ( V (AC) / V (AC) ) for ADD/CMD signals) in every SEH SEL IH IL half-cycle. DQS, DQS have to reach V min / V max (approximately the ac-levels ( V (AC) / V (AC) )
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Rev. 1.0 Unbuffered SODIMM datasheet DDR3 SDRAM 10.3.4 Differential Input Cross Point Voltage To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross point voltage of differential input signals (CK, CK and DQS, DQS) must meet the requirements in below table. The differential input cross point voltage V is measured from the actual IX cross point of true and complement signal to the mid level between of V and V . DD SS V DD CK, DQS V
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Rev. 1.0 Unbuffered SODIMM datasheet DDR3 SDRAM 11. AC & DC Output Measurement Levels 11.1 Single Ended AC and DC Output Levels [ Table 7 ] Single Ended AC and DC output levels Symbol Parameter DDR3-800/1066/1333/1600 Units NOTE V (DC) DC output high measurement level (for IV curve linearity) 0.8 x V V OH DDQ V (DC) DC output mid measurement level (for IV curve linearity) 0.5 x V V OM DDQ V (DC) DC output low measurement level (for IV curve linearity) 0.2 x V V OL DDQ V (AC) AC output high measu
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Rev. 1.0 Unbuffered SODIMM datasheet DDR3 SDRAM 11.4 Differential Output Slew Rate With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between V (AC) and V OLdiff OH- (AC) for differential signals as shown in below. diff [ Table 11 ] Differential Output slew rate definition Measured Description Defined by From To V (AC)-V (AC) OHdiff OLdiff V (AC) V (AC) Differential output slew rate for rising edge OLdiff OHdiff Delta TRdiff V (
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Rev. 1.0 Unbuffered SODIMM datasheet DDR3 SDRAM 12. DIMM IDD specification definition Symbol Description Operating One Bank Active-Precharge Current 1) CKE: High; External clock: On; tCK, nRC, nRAS, CL: Refer to Component Datasheet for detail pattern ; BL: 8 ; AL: 0; CS: High between ACT and PRE; IDD0 Command, Address, Bank Address Inputs: partially toggling ; Data IO: FLOATING; DM:stable at 0; Bank Activity: Cycling with one bank active at a time: 2) 0,0,1,1,2,2,... ; Output Buffer and RTT: E
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Rev. 1.0 Unbuffered SODIMM datasheet DDR3 SDRAM NOTE : 1) Burst Length: BL8 fixed by MRS: set MR0 A[1,0]=00B 2) Output Buffer Enable: set MR1 A[12] = 0B; set MR1 A[5,1] = 01B; RTT_Nom enable: set MR1 A[9,6,2] = 011B; RTT_Wr enable: set MR2 A[10,9] = 10B 3) Precharge Power Down Mode: set MR0 A12=0B for Slow Exit or MR0 A12=1B for Fast Exit 4) Auto Self-Refresh (ASR): set MR2 A6 = 0B to disable or 1B to enable feature 5) Self-Refresh Temperature Range (SRT): set MR2 A7=0B for normal or 1B for exte
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Rev. 1.0 Unbuffered SODIMM datasheet DDR3 SDRAM 13. IDD SPEC Table M471B1G73AH0 : 8GB (1Gx64) Module CF8 CH9 Symbol Unit NOTE (DDR3-1066@CL=7) (DDR3-1333@CL=9) IDD0 600 680 mA 1 IDD1 720 800 mA 1 IDD2P0(slow exit) 240 240 mA IDD2P1(fast exit) 320 320 mA IDD2N 400 480 mA IDD2Q 400 400 mA IDD3P 400 400 mA IDD3N 520 600 mA IDD4R 960 1120 mA 1 IDD4W 1040 1280 mA 1 IDD5B 1440 1600 mA 1 IDD6 240 240 mA IDD7 1520 1880 mA 1 IDD8 240 240 mA NOTE : 1. DIMM IDD SPEC is calculated with considering de-active
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Rev. 1.0 Unbuffered SODIMM datasheet DDR3 SDRAM 14. Input/Output Capacitance 14.1 2Rx8 2GB SODIMM M471B1G73AH0 Parameter Symbol DDR3-1066 DDR3-1333 Units NOTE Min Max Min Max Input/output capacitance CIO - TBD - TBD pF (DQ, DM, DQS, DQS, TDQS, TDQS) Input capacitance (CK and CK) CCK - TBD - TBD pF Input capacitance (All other input-only pins) CI - TBD - TBD pF - 20 -
