Resumen del contenido incluido en la página 1
_ V1.4
User’s Guide
Philips LPC2138 Target Board
Ordering code ITLPC2138
Dimensions 100 x 96 mm
Figure 1: ITLPC2138 Target Board
© iSYSTEM, December 2005 1/16
Resumen del contenido incluido en la página 2
Contents Contents.............................................................................................................................. 2 Introduction ......................................................................................................................... 3 Description .......................................................................................................................... 3 View of the ITLPC2138 ......................................................
Resumen del contenido incluido en la página 3
Introduction Philips LPC2138 Target Board is an evaluation and a development system for Philips ARM7TDMI-S based LPC2138 microcontroller. The ITLPC2138 package consists of a USB cable and a target board populated with Philips LPC2138 CPU, minimum peripherals, JTAG debug connector, ETM trace connector and an on-board integrated iSYSTEM debugger. The user can write and debug the application using the on-board integrated iSYSTEM debugger, which connects to the PC through the USB connection. T
Resumen del contenido incluido en la página 4
Block Diagram Figure 3: ITLPC2138 Block diagram Notes 1. The board provides 16-pin connector for the optional LCD display (type CMC216x04), which is not included in the package. © iSYSTEM, December 2005 4/16
Resumen del contenido incluido en la página 5
Components List Name Description P1 Connector for manufacturing purpose P2 ETM Trace connector P3 JTAG debug connector P4 USB connector (integrated debugger) P5 DB9 connector, serial port (UART1) J1 Expansion connector GPIO pins P0.0 – P0.7 J2 Expansion connector GPIO pins P0.8 – P0.15 J3 Expansion connector GPIO pins P0.16 – P0.23 J4 Expansion connector GPIO pins P0.25 – P0.31 J5 Expansion connector GPIO pins P1.16 – P1.23 J6 Expansion connector GPIO pins P1.24 and P1.25 J7 - J10
Resumen del contenido incluido en la página 6
Power Supply The target board is powered from the PC USB port, through which winIDEA (IDE) running on a PC, connects to the on-board integrated debugger. Connection is made using a standard USB cable. Battery power supply for RTC can be optionally connected to J11 (see J11 description for more details). Jumper & Connector Descriptions • J7: Trace Port Enable: J7 is set to enable pins P1.25:16 to operate as ETM Trace port after reset. Default not set. • J8: Debug Port Enable: J8 is set
Resumen del contenido incluido en la página 7
Connectors DB9 male connector UART1 (P5) Pin No. Symbol 2 RxD 3 TxD 5 GND The serial port is configured as a standard 3-wire interface. Cross female to female cable is needed for connection with PC computer COM port. 3-pin serial connector UART0 (J14) Pin No. Symbol 1 RxD 2 TxD 3 GND The serial port is configured as a standard 3-wire interface. © iSYSTEM, December 2005 7/16
Resumen del contenido incluido en la página 8
16-pin LCD connector (J21) Top View Pin Assignment for Crystal Clear technology CMC216x04 LCD Pin No. Symbol Function 1 GND Ground Terminal 2 Vdd Supply Terminal 3 Vo Power Supply for LCD Driver 4 RS Register Select Signal 5 R/W Read/Write Selection 6 E Enable Signal 7 DB0 Data Bus Line (Not used) 8 DB1 Data Bus Line (Not used) 9 DB2 Data Bus Line (Not used) 10 DB3 Data Bus Line (Not used) 11 DB4 Data Bus Line 12 DB5 Data Bus Line 13 DB6 Data Bus Line 14 DB7 Data Bus Line
Resumen del contenido incluido en la página 9
38-pin Mictor JTAG Debug & ETM Trace Connector (P2) Signal Pin Pin Signal Not used 1 2 Not used Not used 3 4 Not used GND 5 6 TRACECLK Not used 7 8 Not used CPU_RESET 9 10 Not used CPU_TDO 11 12 T3V3 GND 13 14 Not used CTCK 15 16 GND CPU_TMS 17 18 GND CPU_TDI 19 20 GND CPU_TRST 21 22 GND GND 23 24 P1.19 GND 25 26 P1.18 GND 27 28 P1.17 GND 29 30 P1.16 GND 31 32 P1.20 GND 33 34 P1.23 GND 35 36 P1.22 GND 37 38 P1.21 An external JTAG & ETM debug tool can be connected to a 38-
Resumen del contenido incluido en la página 10
Schematic Note: On-board integrated debugger is not part of the schematic. © iSYSTEM, December 2005 10/16
Resumen del contenido incluido en la página 11
Licensing the on-board integrated debugger A 30-days evaluation period starts after the debugger (winIDEA) connects to the ITLPC2138 for the first time. Within the evaluation period, the user should request a regular license from iSYSTEM. Run the request wizard to obtain the license INIT string by pressing the ‘Request INIT…’ button in the ‘Hardware/Hardware/License’ tab. © iSYSTEM, December 2005 11/16
Resumen del contenido incluido en la página 12
Use of the on-board integrated debugger Follow below instructions, in order to get a sample application running with “out of the box” experience. All jumpers are set in the default position during the final tests in the manufacturing. If winIDEA 2006 CD is not part of the package, please obtain winIDEA 2006 setup from your local iSYSTEM office or from www.isystem.com. • Install winIDEA 2006 (IDE) full setup on a PC • Verify jumpers J15-J20 (see Jumpers description for their default positio
Resumen del contenido incluido en la página 13
Use of an external debugger An external debugger can be: • a JTAG debugger, which connects to a 20-pin P3 connector • a development tool supporting JTAG debugging and ETM (on-chip trace), which connects to a 38-pin Mictor P2 connector Setting up a debug environment for the first time • Verify jumpers J15-J20 (see Jumpers description for their default position) • Verify that jumper J8 is set • Verify that jumper J7 is set if your development tool connects to P2 • Verify that jumper J9 is
Resumen del contenido incluido en la página 14
Troubleshooting The flash boot loader code is executed every time the CPU is powered or reset. The loader can execute the ISP command handler or the user application code. P0.14 is sensed on a rising edge on the RST (CPU reset) pin. If a low level is detected, ISP command handler starts and takes over control of the CPU after reset. If there is no request for the ISP command handler execution (a high-level detected), a search is made for a valid user program. If a valid user program is fou
Resumen del contenido incluido en la página 15
Notes: © iSYSTEM, December 2005 15/16
Resumen del contenido incluido en la página 16
Disclaimer: iSYSTEM assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information herein. © iSYSTEM. All rights reserved. © iSYSTEM, December 2005 16/16
