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CY24272
®
Rambus XDR™ Clock Generator with
Zero SDA Hold Time
Features
Table 1. Device Comparison
®
■ Meets Rambus Extended Data Rate (XDR™) clocking
CY24271 CY24272
requirements
SDA hold time = 300 ns SDA hold time = 0 ns
2
■ 25 ps typical cycle-to-cycle jitter
(SMBus compliant) (I C compliant)
❐ –135 dBc/Hz typical phase noise at 20 MHz offset
R = 200 Ω typical R = 295 Ω minimum
RC RC
■ 100 or 133 MHz differential clock input (Rambus standard drive) (Reduced output drive)
■ 300–667 MHz high
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CY24272 CY24272 Pinouts Figure 1. Pin Diagram - 28 Pin TSSOP VDD VDDP 1 28 CLK0 VSSP 2 27 ISET CLK0B 3 26 VSS 4 25 VSS CLK1 REFCLK 5 24 REFCLKB CLK1B 6 23 VDDC VDD 7 22 VSSC VSS 8 21 SCL CLK2 9 20 SDA CLK2B 10 19 EN VSS 11 18 ID0 CLK3 12 17 ID1 CLK3B 13 16 /BYPASS VDD 14 15 Table 2. Pin Definition - 28 Pin TSSOP Pin No. Name IO Description 1 VDDP PWR 2.5V power supply for phased lock loop (PLL) 2 VSSP GND Ground 3 ISET I Set clock driver current (external resistor) 4 VSS GND Ground 5 REFCLK I
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CY24272 PLL Multiplier Table 3 shows the frequency multipliers in the PLL, selectable by programming the SMBus registers MULT0, MULT1, and MULT2. Default multiplier at power up is 4. Table 3. PLL Multiplier Selection Register Output Frequency (MHz) Frequency Multiplier [1] [1] MULT2 MULT1 MULT0 REFCLK = 100 MHz , REFSEL = 0 REFCLK = 133 MHz , REFSEL = 1 0 0 0 3 300 400 [2] 00 1 4 400 – 0 1 0 5 500 667 0 1 1 6 600 – 1 0 0 Reserved – – 1 0 1 9/2 450 600 1 1 0 Reserved – – 1 1 1 15/4 375 500 Inpu
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CY24272 Table 5. Modes of Operation for CY24272 EN /BYPASS RegTest RegA RegB RegC RegD CLK0/CLK0B CLK1/CLK1B CLK2/CLK2B CLK3/CLK3B L X X X X X X High Z High Z High Z High Z H X 1 X X X X Reserved for Vendor Test H L 0 X X X X REFCLK/ REFCLK/ REFCLK/ REFCLK/ [3] REFCLKB REFCLKB REFCLKB REFCLKB H H 0 0 0 0 0 High Z High Z High Z High Z H H 0 0 0 0 1 High Z High Z High Z CLK/CLKB H H 0 0 0 1 0 High Z High Z CLK/CLKB High Z H H 0 0 0 1 1 High Z High Z CLK/CLKB CLK/CLKB H H 0 0 1 0 0 High Z CLK/CLKB
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CY24272 [5] Table 6. Command Code 80h Bit Register POD Type Description 7 Reserved 0 RW Reserved (no internal function) 6 MULT2 0 RW PLL Multiplier Select (reference Table 3 on page 3) 5MULT1 0 RW 4MULT0 1 RW 3 RegA 1 RW Clock 0 Output Select 2 RegB 1 RW Clock 1 Output Select 1 RegC 1 RW Clock 2 Output Select 0 RegD 1 RW Clock 3 Output Select [5] Table 7. Command Code 81h Bit Register POD Type Description 7 Reserved 0 RW Reserved (no internal function) 6 Reserved 0 RW 5 Reserved 0 RW 4 Rese
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CY24272 Figure 2. Differential and Single-Ended Clock Inputs Supply Voltage V TH REFCLKB Input Input REFCLK REFCLK XDR Clock Generator XDR Clock Generator Differential Input Single-ended Input Absolute Maximum Conditions Parameter Description Condition Min Max Unit V Clock Buffer Supply Voltage –0.5 4.6 V DD V Core Supply Voltage –0.5 4.6 V DDC V PLL Supply Voltage –0.5 4.6 V DDP V Input Voltage (SCL and SDA) Relative to V –0.5 4.6 V IN SS Input Voltage (REFCLK/REFCLKB) Relative to V –0.5 V + 1
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CY24272 DC Operating Conditions Parameter Description Condition Min Max Unit V Supply Voltage for PLL 2.5V ± 5% 2.375 2.625 V DDP V Supply Voltage for Core 2.5V ± 5% 2.375 2.625 V DDC V Supply Voltage for Clock Buffers 2.5V ± 5% 2.375 2.625 V DD V Input High Voltage, REFCLK/REFCLKB 0.6 0.95 V IHCLK V Input Low Voltage, REFCLK/REFCLKB –0.15 +0.15 V ILCLK [6] V Crossing Point Voltage, REFCLK/REFCLKB 200 550 mV IXCLK [6] ΔV Difference in Crossing Point Voltage, REFCLK/REFCLKB – 150 mV IXCLK V Input
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CY24272 AC Operating Conditions [6] The AC operating conditions follow. Parameter Description Condition Min Max Unit t REFCLK, REFCLKB input cycle time REFSEL = 0, /BYPASS = High 9 11 ns CYCLE,IN REFSEL = 1, /BYPASS = High 7 8 ns /BYPASS = Low 4 – ns [9] t Input Cycle to Cycle Jitter –185 ps JIT,IN(cc) [10] t Input Duty Cycle Over 10,000 cycles 40% 60% t DCIN CYCLE t / t Rise and Fall Times Measured at 20%–80% of input 175 700 ps RIN FIN voltage for REFCLK and REFCLKB inputs Δt / t Rise and Fal
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CY24272 AC Electrical Specification [6] The AC Electrical specifications follow. Parameter Description Min Typ Max Unit [19] t Clock Cycle time 1.25 3.34 ns CYCLE [20] t Jitter over 1-6 clock cycles at 400–635 MHz –25 40 ps JIT(cc) Jitter over 1-6 clock cycles at 638–667 MHz – 25 30 ps L Phase noise SSB spectral purity L(f) at 20 MHz offset: 400–500 MHz – –135 –128 dBC/Hz 20 6 2.4 (In addition, device must not exceed L(f) = 10log[1+(50x10 /f) ] –138 for f = 1 MHz to 100 MHz except for the regi
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CY24272 Test and Measurement Setup Figure 3. Clock Outputs Measurement V Point V TS T R Z R 1 T1 CH CLK R R C 2 3 R S T2 Swing Current Differential Driver Control ISET Measurement V Point V TS T R RC R Z R 1 CH T1 CLKB R R C 2 3 R S T2 Figure 5 on page 11 shows the definition of the output crossing Example External Resistor Values point. The nominal crossing point between the complementary and Termination Voltages for a 50 Ω Channel outputs is defined as the 50% point of the DC voltage level
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CY24272 Figure 4. Input and Output Waveforms V H 80% V (t) 20% V L t R t F Figure 5. Crossing Point Voltage CLK Vx+ Vx.nom Vx- CLKB Figure 6. Cycle-to-cycle Jitter CLK CLKB t t CYCLE,i CYCLE,i+1 t = t - t J CYCLE,i CYCLE,i+1 over 10,000 consecutive cycles Figure 7. Cycle-to-cycle Duty-cycle Error CLK CLKB t (i) t (i+1) PW- t (i+1) t (i) PW- PW+ PW+ t (i) t (i+1) CYCLE, CYCLE, t = t (i) - t (i+1) and t (i+1) - t (i+1) DC,ERR PW- PW- PW- PW+ Document Number: 001-42414 Rev. ** Page 11 of 13
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CY24272 Ordering Information Part Number Package Type Product Flow Pb-Free CY24272ZXC 28-pin TSSOP Commercial, 0°C to 70°C CY24272ZXCT 28-pin TSSOP – Tape and Reel Commercial, 0°C to 70°C Package Drawing and Dimension Figure 8. 28-Pin Thin Shrunk Small Outline Package (4.40-mm Body) ZZ28 PIN 1 ID 1 6.25[0.246] 6.50[0.256] 4.30[0.169] 4.50[0.177] 28 0.65[0.025] BSC. 1.10[0.043] MAX. 0.25[0.010] 0.19[0.007] 0.30[0.012] BSC GAUGE 0°-8° PLANE 0.076[0.003] 0.50[0.020] 0.85[0.033] 0.05[0.002] 0.09[[0
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CY24272 Document History Page ® Document Title: CY24272 Rambus XDR™ Clock Generator with Zero SDA Hold Time Document Number: 001-42414 Issue Orig. of REV. ECN NO. Description of Change Date Change ** 1749003 See ECN KVM/AESA New data sheet No 8 or 15/2 multipliers or 133MHz * 4 option Max frequency is 667MHz © Cypress Semiconductor Corporation, 2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of a
