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.
ERTEC 200
Enhanced Real-Time Ethernet Controller
Manual
Copyright © Siemens AG 2007. All rights reserved. Page 1 ERTEC 200 Manual
Technical data subject to change Version 1.1.0
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Edition (04/2007) Disclaimer of Liability We have checked the contents of this manual for agreement with the hardware and software described. Since deviations cannot be precluded entirely, we cannot guarantee full agreement. However, the data in this manual are reviewed regularly. Necessary corrections are included in subsequent editions. Suggestions for improvement are welcomed. Copyright © Siemens AG 2006. All rights reserved The reproduction, tra
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Preface Target Audience of this Manual This manual is intended for hardware developers who want to use the ERTEC 200 for new products. Experience working with processors and designing embedded systems and knowledge of Ethernet are required for this. It described all ERTEC function groups in details and provides information that you must take into account when configuring your own PROFINET IO device hardware. The manual serves as a reference for software developers. The address
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This manual will be updated as required. You can find the current version of the manual on the Internet at http://www.siemens.com/comdec. Guide To help you quickly find the information you need, this manual contains the following aids: o A complete table of contents as well as a list of all figures and tables in the manual are provided at the beginning of the manual. o A glossary containing definitions of important terms used in the manual is located following the appendices.
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Contents 1 Introduction ............................................................................................................................9 1.1 Applications of the ERTEC 200.............................................................................................................. 9 1.2 Features of the ERTEC 200 ................................................................................................................... 9 1.3 Structure of the ERTEC 200....................
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4.4.2 F-Timer Register Description ......................................................................................................... 44 4.5 Watchdog Timers ................................................................................................................................... 45 4.5.1 Watchdog Timer 0.......................................................................................................................... 45 4.5.2 Watchdog Timer 1..........................
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11.1.3 ETM9 Registers ............................................................................................................................. 94 11.2 Trace Interface ....................................................................................................................................... 95 11.3 JTAG Interface ....................................................................................................................................... 95 11.4 Debugging via UART..
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List of Figures Figure 1: ERTEC 200 Block Diagram .................................................................................................................... 10 Figure 2: ERTEC 200 Package Description .......................................................................................................... 11 Figure 3: Structure of ARM946E-S Processor System .......................................................................................... 21 Figure 4: GPIO Cell on GPI
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1 Introduction The ERTEC 200 is intended for the implementation of PROFINET devices with RT and IRT functionality. With its integrated ARM946 processor and 2-port Ethernet switch with integrated PHYs and the option to connect an external host processor system to a local bus interface, it meets all the requirements for implementing PROFINET devices with integrated switch functionality. 1.1 Applications of the ERTEC 200 Interface connection for high-precision drive control, including
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1.3 Structure of the ERTEC 200 The figure below shows the function groups with the common communication paths. External LBU / MII + SMI / 25MHz TRACE_ REF_ Memory Interface JTAG / Debug F_CLK ETM / GPIO CLK CLK 1 1 48 1 1 7 1 Reset MUX 74 ARM946ES Clock-Unit PLL 4 Test 1 BS- 48 with ARM- TAP DMA- I-Cache (8kByte), Interrupt- Local Memory- Controller Bus Unit D-Cache (4kByte), Controller ETM Controller 16 Bit APB Interface D-TCM (4kByte) (EMIF) 50MHz / 32 Bit (LBU) Master Master Sla
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1.4 ERTEC 200 Package The ERTEC 200 is supplied in an FBGA package with 304 pins. The distance between the pins is 0.8 mm. The package dimensions are 19 mm x 19 mm. Figure 2: ERTEC 200 Package Description Soldering instructions for the ERTEC 200 can be found in the following documents: /10/ Soldering instructions for lead-based block. /11/ Soldering instructions for lead-free block. /12/ Code description for soldering. When working with modules, always take precautionary measur
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1.5 Signal Function Description ERTEC 200 Pin Description The ERTEC 200 Ethernet communication block is available in a 304-pin FBGA package. The signal names of the ERTEC 200 are described in this section. 1.5.1 GPIO 0 to 31 and Alternative Functions Various signals are multiplexed on the same pin. These multiplexed signals can contain up to four different functions. The alternative functions are assigned in GPIO registers GPIO_PORT_MODE_L and GPIO_PORT_MODE_H (see Section 4.2.2). The
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No. Signal Alternative Alternative Alternative I/O Pull- PIN Comment Name Function 1 Function 2 Function 3 (Reset) No. General Purpose I/O / I/O 23 GPIO22 SPI1_SFRMIN DBGACK B/I/O/(I) up F10 GPIO or SPI1 (I) or Debug (O) This GPIO is used as chip select when booting from Nand Flash or SPI ROM. 24 GPIO23 SPI1_SCLKIN Reserved B/I/O/(I) up D10 GPIO or SPI1 (I) This GPIO is used as chip select when booting from SPI Flash or SPI EEPROM. 25 GPIO24 PLL_EXT_IN_N B/I (I)
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1.5.4 Clock and Reset No. Signal Name I/O Pull- PIN Comment (Reset) No. CLOCK / RESET GENERATION 42 CLKP_A I (I) B14 Quartz connection 43 CLKP_B O D14 Quartz connection 44 F_CLK I (I) B13 F_CLK for F-counter 45 REF_CLK Dependent A15 Tristate or on PIN reference clock output, 25 MHz CONFIG[1] 46 RESET_N I (I) up B7 PowerOn reset 1.5.5 Test Pins No. Signal Name I/O Pull- PIN Comment (Reset) No. TEST 47 TEST_N (3) I (I) up T5 Test mode 48 TMC1 (3) I (I)
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No. Signal Name Alternative I/O Pull- PIN Comment Reset Function (Reset) No. EMIF (External Memory Interface) 66 A13 G2 Address bit 13 O (O) SDRAM: Address 11 67 A14 G1 Address bit 14 O (O) SDRAM: Address 12 68 A15 BOOT1 B (I) dn H2 Address bit 15 ERTEC 200 boot mode (ext. PU may be necessary) 69 A16 BOOT2 B (I) dn J2 Address bit 16 / ERTEC 200 boot mode (ext. PU may be necessary) 70 A17 BOOT3 B (I) up K2 Address bit 17 / ERTEC 200 boot mode (ext. PD may be
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No. Signal Name Alternative I/O Pull- PIN Comment Reset Function (Reset) No. EMIF (External Memory Interface) 109 WR_N O (O) A4 Write strobe 110 RD_N O (O) B5 Read strobe 111 CS_PER0_N D5 Chip Select Bank 1 (ROM); O (O) boot area 112 CS_PER1_N O (O) A5 Chip select bank 2 113 CS_PER2_N O (O) A6 Chip select bank 3 114 CS_PER3_N O (O) B6 Chip select bank 4 115 BE0_DQM0_N O (O) N4 Byte enable 0 for D(7:0) 116 BE1_DQM1_N O (O) V1 Byte enable 1 for D
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No. Function 1 Function 2 Function 3 Function 4 IO Pull PIN Comment LBU PHY Debug ETM Trace (Reset - No. and and See GPIO[44:32] GPIO[44:32] Reserved Config Config Config Config [6,5,2]) (6,5,2)=xx0b (6,5,2)=011b (6,5,2)=101b [6,5,2]=111b LBU / MII-Interface 141 LBU_A16 GPIO32 GPIO32 I/B/B/B up W9 LBU or GPIO (GPIO:I) 142 LBU_A17 GPIO33 GPIO33 I/B/B/B up W10 LBU or GPIO (GPIO:I) 143 LBU_A18 GPIO34 GPIO34 I/B/B/B up V10 LBU or GPIO (GPIO:I) 144 LBU_A19 GPIO35 G
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No. Function 1 Function 2 Function 3 Function 4 IO Pull PIN Comment LBU PHY Debug ETM Trace (Reset - No. and and See GPIO[44:32] GPIO[44:32] Reserved Config Config Config Config [6,5,2]) (6,5,2)=xx0b (6,5,2)=011b (6,5,2)=101b [6,5,2]=111b LBU / MII-Interface 166 LBU_D12 SMI_MDC B/O/I/O up W14 LBU or MII (LBU : I) 167 LBU_D13 SMI_MDIO B/O/I/O up V15 LBU or MII (LBU : I) 168 LBU_D14 RES_PHY_N B/O/I/O up V16 LBU or MII (LBU : I) 169 LBU_D15 GPIO41 GPIO41 B/B
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No. Signal Name I/O Pull- PIN Comment No. PHY1 and PHY2 196 P1SDxN I F19 Port1 FX differential SD input 197 P1SDxP I G19 Port1 FX differential SD input 198 P1TDxN O C22 Port1 FX differential transmit output 199 P1TDxP O C21 Port1 FX differential transmit output 200 P1RDxN I E21 Port1 FX differential receive input 201 P1RDxP I E22 Port1 FX differential receive input 202 P1VSSATX2 I K18 Analog port GND supply 203 P1TxP B J22 Port1 differential tran
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Signal description: IO = Signal direction from perspective of the application I: Input O: Output B: Bidirectional P: Power supply Pull- = Internal pull-up/pull-down resistor connected to the signal pin up: Internal pull-up dn: Internal pull-down PU/PD = External resistances necessary, depending on application PU: External pull-up PD: External pull-down _N in last position of signal name signifies: Signal is Low active Example: INTA_N Note: (1) The
