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Intel® PXA255 Processor
Developer’s Manual
March, 2003
Order Number: 278693-001
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INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE,
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Contents Contents 1 Introduction...................................................................................................................................1-1 1.1 Intel® XScale™ Microarchitecture Features......................................................................1-1 1.2 System Integration Features..............................................................................................1-1 1.2.1 Memory Controller .............................................................
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Contents 3.3.1 32.768 kHz Oscillator............................................................................................3-4 3.3.2 3.6864 MHz Oscillator ..........................................................................................3-4 3.3.3 Core Phase Locked Loop .....................................................................................3-4 3.3.4 95.85 MHz Peripheral Phase Locked Loop ..........................................................3-5 3.3.5 147.46 MHz Peri
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Contents 4.2 Interrupt Controller...........................................................................................................4-20 4.2.1 Interrupt Controller Operation .............................................................................4-20 4.2.2 Interrupt Controller Register Definitions..............................................................4-21 4.3 Real-Time Clock (RTC) ................................................................................................
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Contents 6.2.1 SDRAM Interface Overview..................................................................................6-2 6.2.2 Static Memory Interface / Variable Latency I/O Interface .....................................6-3 6.2.3 16-Bit PC Card / Compact Flash Interface ...........................................................6-4 6.3 Memory System Examples................................................................................................6-4 6.4 Memory Accesses ...............
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Contents 7.2.2 Disabling the Controller ........................................................................................7-5 7.2.3 Resetting the Controller ........................................................................................7-5 7.3 Detailed Module Descriptions ............................................................................................7-5 7.3.1 Input FIFOs...................................................................................................
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Contents 9.3.1 Operational Blocks................................................................................................9-3 9.3.2 I2C Bus Interface Modes .....................................................................................9-3 9.3.3 Start and Stop Bus States ....................................................................................9-4 9.4 I2C Bus Operation ..........................................................................................................
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Contents 11.2 FICP Operation................................................................................................................11-1 11.2.1 4PPM Modulation ...............................................................................................11-2 11.2.2 Frame Format .....................................................................................................11-3 11.2.3 Address Field......................................................................................
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Contents 12.6.1 UDC Control Register (UDCCR).......................................................................12-22 12.6.2 UDC Control Function Register (UDCCFR)......................................................12-24 12.6.3 UDC Endpoint 0 Control/Status Register (UDCCS0) .......................................12-25 12.6.4 UDC Endpoint x Control/Status Register (UDCCS1/6/11)................................12-27 12.6.5 UDC Endpoint x Control/Status Register (UDCCS2/7/12)..................
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Contents 14.3.1 Initialization .........................................................................................................14-3 14.3.2 Disabling and Enabling Audio Replay.................................................................14-4 14.3.3 Disabling and Enabling Audio Record ................................................................14-4 14.3.4 Transmit FIFO Errors..........................................................................................14-5 14.3.5 Receiv
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Contents 15.4.11 Stream Read.....................................................................................................15-21 15.5 MMC Controller Registers .............................................................................................15-22 15.5.1 MMC_STRPCL Register...................................................................................15-22 15.5.2 MMC_Status Register (MMC_STAT) ...............................................................15-23 15.5.3 MMC_CLK
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Contents 17.4.3 Autoflow Control .................................................................................................17-7 17.4.4 Auto-Baud-Rate Detection..................................................................................17-7 17.4.5 Slow Infrared Asynchronous Interface................................................................17-8 17.5 Register Descriptions.....................................................................................................17-10 17
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Contents 6-14 Flash Memory Reset Using State Machine .............................................................................6-42 6-15 Flash Memory Reset Logic if Watchdog Reset is Not Necessary ...........................................6-42 6-16 MSC0/1/2.................................................................................................................................6-45 6-17 32-Bit Burst-of-Eight ROM or Flash Read Timing Diagram (MSC0[RDF] = 4, MSC0[RDN] = 1, MSC0[RRR] = 1)
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Contents 9-2 Start and Stop Conditions..........................................................................................................9-5 9-3 START and STOP Conditions ...................................................................................................9-6 9-4 Data Format of First Byte in Master Transaction.......................................................................9-8 9-5 Acknowledge on the I2C Bus...............................................................
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Contents 16-6 Motorola SPI* Frame Protocols for SPO and SPH Programming (single transfers) .................................................................................................................................16-9 16-7 National Semiconductor Microwire* Frame Protocol (multiple transfers) ..............................16-10 16-8 National Semiconductor Microwire* Frame Protocol (single transfers) .................................16-10 16-9 Programmable Serial Protocol (multiple transfe
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Contents 3-21 CKEN Bit Definitions................................................................................................................3-36 3-22 OSCC Bit Definitions ...............................................................................................................3-38 3-23 Coprocessor 14 Clock and Power Management Summary.....................................................3-39 3-24 CCLKCFG Bit Definitions...................................................................
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Contents 4-44 OSCR Bit Definitions ...............................................................................................................4-37 4-45 OSSR Bit Definitions ...............................................................................................................4-38 4-46 PWM_CTRLn Bit Definitions ...................................................................................................4-41 4-47 PWM_DUTYn Bit Definitions .........................................
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Contents 6-28 Common Memory Space Write Commands ............................................................................6-63 6-29 Common Memory Space Read Commands............................................................................6-63 6-30 Attribute Memory Space Write Commands .............................................................................6-63 6-31 Attribute Memory Space Read Commands .............................................................................6-63 6-
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Contents 10-3 RBR Bit Definitions ..................................................................................................................10-6 10-4 THR Bit Definitions ..................................................................................................................10-7 10-5 DLL Bit Definitions ...................................................................................................................10-8 10-6 DLH Bit Definitions .................................
