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TMS320C6472/TMS320TCI6486 DSP
Ethernet Media Access Controller (EMAC)/
Management Data Input/Output (MDIO) Module
User's Guide
Literature Number: SPRUEF8F
March 2006–Revised November 2010
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2 SPRUEF8F–March 2006–Revised November 2010 Submit Documentation Feedback Copyright © 2006–2010, Texas Instruments Incorporated
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Preface ...................................................................................................................................... 10 1 Introduction ...................................................................................................................... 11 1.1 Purpose of the Peripheral ............................................................................................. 11 1.2 Features .............................................................................
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www.ti.com 4.11 MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) ................. 86 4.12 MDIO User Access Register 0 (USERACCESS0) ................................................................ 87 4.13 MDIO User PHY Select Register 0 (USERPHYSEL0) ............................................................ 88 4.14 MDIO User Access Register 1 (USERACCESS1) ................................................................ 89 4.15 MDIO User PHY Select Register 1 (USER
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www.ti.com 5.43 MAC Address Low Bytes Register (MACADDRLO) ............................................................. 141 5.44 MAC Address High Bytes Register (MACADDRHI) ............................................................. 142 5.45 MAC Index Register (MACINDEX) ................................................................................. 143 5.46 Transmit Channel 0-7 DMA Head Descriptor Pointer Register (TXnHDP) ................................... 144 5.47 Receive Channel 0-7 DM
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www.ti.com List of Figures 1 EMAC and MDIO Block Diagram........................................................................................ 12 2 Ethernet Configuration with MII Interface .............................................................................. 18 3 Ethernet Configuration with RMII Interface ............................................................................ 20 4 Ethernet Configuration with GMII Interface ........................................................
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www.ti.com 48 Receive Teardown Register (RXTEARDOWN)...................................................................... 100 49 Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW).............................................. 101 50 Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) ............................................ 102 51 Transmit Interrupt Mask Set Register (TXINTMASKSET).......................................................... 103 52 Transmit Interrupt Mask C
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www.ti.com List of Tables 1 Serial Management Interface Pins ...................................................................................... 13 2 EMAC1_EN Pin Description ............................................................................................. 13 3 EMAC Clock Specifications .............................................................................................. 15 4 EMAC0 Interface Selection Pins ..................................................................
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www.ti.com 47 MAC Input Vector Register (MACINVECTOR) Field Descriptions ................................................ 105 48 MAC End-of-Interrupt Vector Register (MACEOIVECTOR) Field Descriptions.................................. 106 49 Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) Field Descriptions........................ 107 50 Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) Field Descriptions ...................... 108 51 Receive Interrupt Mask Set Register (RX
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Preface SPRUEF8F–March 2006–Revised November 2010 Read This First About This Manual This document provides a functional description of the Ethernet Media Access Controller (EMAC) and Physical layer (PHY) device Management Data Input/Output (MDIO) module integrated with TMS320TCI6486/TMS320C6472 devices. Included are the features of the EMAC and MDIO modules, a discussion of their architecture and operation, how these modules connect to the outside world, and the registers descriptions for each m
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User's Guide SPRUEF8F–March 2006–Revised November 2010 C6472/TCI6486 EMAC/MDIO 1 Introduction This document provides a functional description of the Ethernet Media Access Controller (EMAC) and Physical layer (PHY) device Management Data Input/Output (MDIO) module integrated with TMS320TCI6486/TMS320C6472 devices. Included are the features of the EMAC and MDIO modules, a discussion of their architecture and operation, how these modules connect to the outside world, and the registers descriptions
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Introduction www.ti.com • Single MDIO, shared by both EMAC modules. 1.3 Functional Block Diagram Figure 1 shows the functional block diagram of the EMAC peripherals used in the TCI6486/C6472 device. It consists mainly of: • EMAC0 • EMAC1 • CPPI buffer manager per EMAC • EMIC per EMAC • MDIO Figure 1. EMAC and MDIO Block Diagram To GEMs EMAC Control 0 Module EMIC0 DMA MII0/GMII0 memory transfer control CPPI buffer S3MII0 EMAC0 manager + CPPI RAM0 RMII0 RGMII0 Peripheral bus MDIO To PHYs CPPI buff
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www.ti.com Introduction The EMAC module provides an efficient interface between the TCI6486/C6472 core processor and the networked community. The EMAC supports 10Base-T (10 Mbits/sec) and 100Base-TX (100 Mbits/sec) in either half- or full-duplex mode, and 1000Base-T (1000 Mbits/sec) in full-duplex mode, with hardware flow control and quality-of-service (QOS) support. Each EMAC module has a communications port programming interface (CPPI) buffer manager to manage 8K of CPPI RAM. The EMAC uses fou
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Introduction www.ti.com Table 2. EMAC1_EN Pin Description (continued) Value Description 1 EMAC1 is enabled and used. Pulls on EMAC1 I/O are disabled (except RGMII pins) and the corresponding I/O buffers are powered up except RGMII output-only pins. NOTE: RGMII buffers are HSTL buffers with no internal pulls. RGMII output only pins will always be powered down even when the module is enabled. EMAC1_EN is also software programmable through the DEVCTL register. A write to the DEVCTL register is key-
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www.ti.com EMAC Functional Architecture 2 EMAC Functional Architecture This section discusses the architecture and basic function of the EMAC peripheral. 2.1 Clock Control The frequencies for the transmit and receive clocks are fixed by the IEEE 802.3 specification, as shown below: • 2.5 MHz at 10 Mbps • 25 MHz at 100 Mbps • 125 MHz at 1000 Mbps All clock sources, with the exception of the EMAC peripheral bus clock, are sourced from the PLL2 controller. The PLL2 controller has 3 clocks for EMAC0
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EMAC Functional Architecture www.ti.com 2.1.3 GMII Clocking The GMII interface is available only on EMAC0 and requires two clock sources generated internally, the peripheral bus clock and the RFTCLK inputs to the EMAC module. SYSCLK14 is programmed to /4 for this interface to provide a 125-MHz clock to the RFTCLK input of EMAC. The GMII interface is selected by programming MACSEL0 to 2 (010b). Transmit and receive clock sources for 10/100-Mbps modes are provided from an external PHY via the MTCL
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www.ti.com EMAC Functional Architecture 2.3 System-Level Connections On the TCI6486/C6472 device, EMAC0 and EMAC1 support the following different types of interfaces to physical layer devices (PHYs) or switches. Each EMAC can be configured to only one interface at any given time. EMAC0 interface is selected by programming MACSEL0 [2:0] pins (see Table 4) and EMAC1 interface is selected by programming MACSEL1 [1:0] pins (see Table 5). Table 4. EMAC0 Interface Selection Pins MACSEL0 [2:0] Interfac
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EMAC Functional Architecture www.ti.com Table 6. MACSEL0[2:0], MACSEL1[1:0], and EMAC1_EN Decoding (continued) MACSEL02 MACSEL01 MACSEL00 MACSEL11 MACSEL10 EMAC_EN EMAC0 EMAC1 1 0 0 1 1 1 None RMII 1 0 1 0 0 1 S3MII None 1 0 1 0 1 1 S3MII S3MII 1 0 1 1 0 1 S3MII RGMII 1 0 1 1 1 1 S3MII RMII 1 1 1 X X 0 None None 1 1 1 0 0 1 None None 1 1 1 0 1 1 None S3MII 1 1 1 1 0 1 None RGMII 1 1 1 1 1 1 None RMII 2.3.1 Media Independent Interface (MII) Connections Figure 2 shows a TCI6486/C6472 device with i
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www.ti.com EMAC Functional Architecture Table 7. EMAC and MDIO Signals for MII Interface Signal Name I/O Description MTCLK I Transmit clock (MTCLK). The transmit clock is a continuous clock that provides the timing reference for transmit operations. The MTXD and MTXEN signals are tied to this clock. The clock is generated by the PHY and is 2.5 MHz at 10-Mbps operation and 25 MHz at 100-Mbps operation. MTXD[3:0] O Transmit data (MTXD). The transmit data pins are a collection of 4 data signals com
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EMAC Functional Architecture www.ti.com 2.3.2 Reduced Media Independent Interface (RMII) Connections Figure 3 shows a TCI6486/C6472 device with integrated EMAC and MDIO interfaced to the PHY via an RMII connection. This interface is available only in 10-Mbps and 100-Mbps modes. Figure 3. Ethernet Configuration with RMII Interface 50-MHz 50-MHz zero-delay XO clock buffer RMREFCLK RMREFCLK RMTXD[1−0] RMTXEN RMCRSDV Physical layer System RMRXD[1−0] device core (PHY) RMRXER MDCLK MDIO The RMII inter
