Resumen del contenido incluido en la página 1
TMS320DM643x DMP
VLYNQ Port
User's Guide
Literature Number: SPRU938B
September 2007
Resumen del contenido incluido en la página 2
2 SPRU938B–September 2007 Submit Documentation Feedback
Resumen del contenido incluido en la página 3
Contents Preface ............................................................................................................................... 7 1 Introduction................................................................................................................ 8 1.1 Purpose of the Peripheral....................................................................................... 8 1.2 Features.............................................................................................
Resumen del contenido incluido en la página 4
A.2 Special 8b/10b Code Groups ................................................................................. 39 A.3 Supported Ordered Sets....................................................................................... 39 A.4 VLYNQ 2.0 Packet Format.................................................................................... 40 A.5 VLYNQ 2.X Packets............................................................................................ 42 Appendix B Write/Read Performance .
Resumen del contenido incluido en la página 5
List of Figures 1 VLYNQ Port Functional Block Diagram................................................................................... 9 2 External Clock Block Diagram............................................................................................ 10 3 Internal Clock Block Diagram............................................................................................. 10 4 VLYNQ Module Structure ...................................................................................
Resumen del contenido incluido en la página 6
List of Tables 1 VLYNQ Signal Descriptions............................................................................................... 11 2 Address Translation Example (Single Mapped Region) .............................................................. 17 3 Address Translation Example (Single Mapped Region) .............................................................. 18 4 VLYNQ Register Address Space......................................................................................... 2
Resumen del contenido incluido en la página 7
Preface SPRU938B–September 2007 Read This First About This Manual This document describes the VLYNQ port in the TMS320DM643x Digital Media Processor (DMP). Notational Conventions This document uses the following conventions. • Hexadecimal numbers are shown with the suffix h. For example, the following number is 40 hexadecimal (decimal 64): 40h. • Registers in this document are shown in figures and described in tables. – Each register figure shows a rectangle divided into fields that represent th
Resumen del contenido incluido en la página 8
User's Guide SPRU938B–September 2007 VLYNQ Port 1 Introduction 1.1 Purpose of the Peripheral The VLYNQ™ communications interface port is a low pin count, high-speed, point-to-point serial interface in the TMS320DM643x Digital Media Processor (DMP) used for connecting to host processors and other VLYNQ compatible devices. The VLYNQ port is a full-duplex serial bus where transmit and receive operations occur separately and simultaneously without interference. VLYNQ enables the extension of an inte
Resumen del contenido incluido en la página 9
www.ti.com Introduction • Symmetric Operations – Transmit (TX) pins on the first device connect to the receive (RX) pins on the second device and vice-versa. – Data pin widths are automatically detected after reset – Re-request packets, response packets, and flow control information are all multiplexed and sent across the same physical pins. – Supports both host/peripheral and peer-to-peer communication models • Simple block code packet formatting (8b/10b) • Supports in-band and flow control – N
Resumen del contenido incluido en la página 10
www.ti.com Peripheral Architecture 2 Peripheral Architecture This section discusses the architecture and basic functions of the VLYNQ peripheral. 2.1 Clock Control The module's serial clock direction and frequency are software configurable through the CLKDIR and CLKDIV bits in the VLYNQ control register (CTRL). The VLYNQ serial clock can be sourced from the internal system clock (CLKDIR = 1) or by an external clock source (CLKDIR = 0) for its serial operations. The CLKDIV bit can divide the seri
Resumen del contenido incluido en la página 11
www.ti.com Peripheral Architecture 2.2 Signal Descriptions The VLYNQ module on the DM643x device supports 1 to 4 bit-wide RX/TX configurations. Chip-level pin multiplexing registers control the configuration. See the pin multiplexing information in the device-specific data manual. If the VLYNQ data width does not match the number of transmit/receive lines that are available on the remote device, negotiation between the two VLYNQ devices automatically configures the width (see Section 2.7). The V
Resumen del contenido incluido en la página 12
www.ti.com Peripheral Architecture 2.5 VLYNQ Functional Description The VLYNQ core supports both host-to-peripheral and peer-to-peer communication models and is symmetrical. The VLYNQ module structure is shown in Figure 4. Figure 4. VLYNQ Module Structure System clock VLYNQ clock Outbound Slave Address Outbound 8B/10B Serial config bus command TxSM Serializer translation commands encoding TxData interface FIFO Serial (FIFO3) TxClk Return data FIFO Registers (FIFO2) Return data FIFO Serial (FIFO0
Resumen del contenido incluido en la página 13
www.ti.com Peripheral Architecture 2.5.1 Write Operations Write requests that initiate from the slave configuration bus interface of the local device write to the outbound command (CMD) FIFO. Data is subsequently read from the FIFO and encapsulated in a write request packet. The address is translated, and the packet is encoded and serialized before being transmitted to remote device. The remote device subsequently deserializes and decodes the receive data and writes it into the inbound CMD FIFO.
Resumen del contenido incluido en la página 14
www.ti.com Peripheral Architecture 2.5.2 Read Operations Read requests from the slave configuration bus interface are written to the outbound CMD FIFO (similar to the write requests). Data is subsequently read from the FIFO and encapsulated into a read request packet. The packet is encoded and serialized before it is transmitted to the remote device. Next, the remote device deserializes, decodes the receive data, and writes the receive data to the inbound CMD FIFO. After reading the address from
Resumen del contenido incluido en la página 15
www.ti.com Peripheral Architecture Note: Not servicing read operations results in deadlock. The only way to recover from a deadlock situation is to perform a hard reset. Read operations are typically not serviced due to read requests that are issued to a non-existent remote VLYNQ device or they are not serviced due to trying to perform reads on the VLYNQ memory map prior to establishing the link. Generally, you should not use read operations to transfer data packets since the serial nature of th
Resumen del contenido incluido en la página 16
www.ti.com Peripheral Architecture 2.8 Address Translation Remote VLYNQ device(s) are memory mapped to the local (host) device’s address space when a link is established (this is similar to any other on-chip peripherals). Enumerating the VLYNQ devices (single or multiple) into a coherent memory map for accessing each device is part of the initialization sequence. After the enumeration, the host (local) device can access the remote device address map using local device addresses. The VLYNQ module
Resumen del contenido incluido en la página 17
www.ti.com Peripheral Architecture Figure 7. Example Address Memory Map Remote DMxxx device (local) VLYNQ device 0000:0000h Map region 1 0400:0000h (4C00:0000h on DM643x device) 03FF:FFFFh Map region 1 0400:0000h Map region 2 07FF:FFFFh 0400:00FFh 0800:0000h Map region 2 0800:00FFh 0500:0000h 0800:0100h Map region 3 Map region 3 0801:00FFh 0500:FFFFh 0801:0100h Map region 4 0B00:0000h Map region 4 0841:00FFh 0B3F:FFFFh The following shows an example illustrating the address translation used in e
Resumen del contenido incluido en la página 18
www.ti.com Peripheral Architecture DM643x VLYNQ Module: 4C00 : 0054h Initial address at the slave configuration bus 0000 : 0054h Initial address [25:0] at the slave configuration bus interface subtract 0000 : 0000h TX address map register (there is no need to change the reset value of the DM643x device for this register) 0000 : 0054h Remote VLYNQ Module: 0000 : 0054h Initial address from the RX serial interface compare 0000 : 0100h RX address map size 1 register 0000 : 0054h add 0800 : 0000h RX
Resumen del contenido incluido en la página 19
www.ti.com Peripheral Architecture Example 1. Address Translation Example The remote address 0400:0154h (or 0000 0054h) was translated to 8200:0054h on the DM643x (local) device in this example. The translated address for packets received on the serial interface is determined as follows: If (RXPacketAddress< RXAddressMapSize1 Register) { Translated Address = RX Packet Address + RX Address Map Offset 1 Register } else if (RXPacketAddress<(RX AddressMapSize1Register+ RXAddressMapSize 2Register)) {
Resumen del contenido incluido en la página 20
www.ti.com Peripheral Architecture 2.10 Reset Considerations 2.10.1 Software Reset Considerations Peripheral clock and reset control is done through the power and sleep controller (PSC) module that is included with the device. For more information, see Section 2.13. Additionally, there is a software reset (the reset bit in the VLYNQ control register, CTRL) within the peripheral itself. Writing a 1 to the reset bit resets all of the internal state machines of the VLYNQ module, the serial interfac
