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REG10J0052-0200
Renesas Starter Kit Ethernet & USB
Application Board User's Manual
RENESAS STARTER KIT
Rev.2.00 Renesas Technology Europe Ltd.
Revision date：17.Jan.2008 www.renesas.com
D007133_11
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Table of Contents Chapter 1. Preface..................................................................................................................................................3 Chapter 2. Purpose.................................................................................................................................................4 Chapter 3. Board Layout.........................................................................................................................
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Chapter 1. Preface Cautions This document may be, wholly or partially, subject to change without notice. All rights reserved. Duplication of this document, either in whole or part is prohibited without the written permission of Renesas Technology Europe Limited. Trademarks All brand or product names used in this manual are trademarks or registered trademarks of their respective companies or organisations. Copyright © Renesas Technology Europe Ltd. 2007. All rights reserved. Website:
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Chapter 2.Purpose This RSK Application Board is an evaluation tool for using Renesas microcontrollers with Ethernet and USB interfaces. It is used in conjunction with the RSK for the microcontroller to be evaluated. Features include: • Mounting connections to allow RSK to be added to top of board. • Interface to standard RSK ‘Application Interface’ connectors. • Interface to Memory Expansion connectors. • Power connector for +5V (reverse polarity protected), with on-board regulated 3.3V
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Chapter 3.Board Layout 3.1.Component References The following diagram shows the component references for the board. Figure 3-1: Component References 5
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3.2.Board Component functions The following diagram the shows the functions of the components on the board. +5V DC Application Board Interface JA5 JA1 USB J4 J1 Mini AB J5 USB Std A J3 JA3 RJ45 J2 JA6 JA2 Memory Extension Interface Application Board Interface Figure 3-2: Board Layout 6
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3.3.Board Dimensions The following diagram gives the board dimensions and connector positions. All through hole connectors are on a common 0.1” grid for easy interfacing. Figure 3-3 : Board Dimensions 7
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Chapter 4.User Circuitry 4.1.Fitting the Target RSK to the RSK application board The board is supplied with 2x 24 way sockets, 2x 26 way sockets and 1 x 50 way socket. These should be soldered on the underside of the host RSK in JA1, JA2, JA5, JA6 and JA3 positions. The RSK should be plugged into the equivalent connectors on the RSK LCD application board. A separate application note is available to explain how to configure the host RSK to enable it to connect to this application board.
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5ns A[7:1] 5ns 35ns CSn,WRn 10ns 5ns Data Valid Figure 4-2: Ethernet controller write timing The Ethernet controller can drive two interrupts. IRQ0 is the IRQ from the Ethernet controller. IRQ2 is the PME output from the Ethernet controller. PME interrupts can be enabled on the IRQ pin, so this can be disabled for host RSKs with fewer interrupt lines, if the PME interrupt is required. Both interrupts are pulled high to 3.3V by 1K resistors. 4.3.USB Controller The Universal Serial B
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5ns A[17:1] 5ns 40ns CSn,RDn 35ns 0ns Data Valid Figure 4-3: USB controller read timing 5ns A[17:1] 5ns 20ns CSn,WRn 8ns 5ns Data Valid Figure 4-4: USB controller write timing The ISP1761 controller can drive two interrupts. IRQ1 is the HC_IRQ from the ISP1761 controller. IRQ3 is the DC_IRQ output from the ISP1761 controller. DC_IRQ interrupts can be enabled on the HC_IRQ pin, so this can be disabled for host RSKs with fewer interrupt lines, if the DC_IRQ interrupt is required. Both
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4.4.SRAM The board is provided with 512 kilobytes of static RAM arranged as 256k x 16 bit words. This RAM is byte addressable, provided the host RSK supports this. The chip select used for the RAM is CS3 which is on JA3 pin 45. Please note the timing. This will require programming the bus controller for the Host RSK. 5ns A[18:1] 5ns 20ns CSn,RDn 15ns 0ns Data Valid Figure 4-5: SRAM read timing 5ns A[18:1] 5ns 20ns CSn,WRn 8ns 5ns Data Valid Figure 4-6: SRAM write timing 11
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4.5.Option Links Table 4-1 below describes the function of the option links contained on this CPU board. The default configuration is indicated by BOLD text. Option Link Settings Reference Function Fitted Alternative (Removed) Related To R2 3V power select Regulator drives Board_3V3 Board_3V from RSK R7 Write Strobe Select High Byte writes from WR1n WR1n not connected R8, R9, R10 R8 Write Strobe Select High Byte writes from WR1n WR1n not connected R7, R9, R10 R9 Write Strobe Select Lo
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Chapter 5.Headers 5.1.Application Headers This information is supplied for reference. Only pins marked are connected on this board. These connections are not level translated. Table 5-1 and Table 5-2 below show the standard application header connections. JA1 Pin Generic Header Name CPU board Pin Header Name CPU board Signal Name Signal Name 1 Regulated Supply 1 5V 2 Regulated Supply 1 GROUND 3 Regulated Supply 2 3V3 4 Regulated Supply 2 GROUND 5 Analogue Supply AVcc 6 Ana
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JA2 Pin Generic Header Name CPU board Pin Header Name CPU board Signal Name Signal Name 1 Open drain RESn 2 External Clock Input EXTAL 3 Open drain NMIn 4 Regulated Supply 1 Vss1 5 Open drain output WDT_OVF 6 Serial Port SCIaTX 7 Open drain WUP IRQ0 8 Serial Port SCIaRX 9 Open drain IRQ1 10 Serial Port SCIaCK 11 Up/down MO_UD 12 Serial Port Handshake CTS/RTS 13 Motor control MO_Up 14 Motor control MO_Un 15 Motor control MO_Vp 16 Motor control MO_Vn 17 Motor control MO_Wp 18
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JA6 Pin Generic Header Name CPU board Pin Header Name CPU board Signal Signal Name Name 1 DMA DREQ 2 DMA DACK 3 DMA TEND 4 Standby (Open drain) STBYn 5 Host Serial SCIdTX RS232TX 6 Host Serial SCIdRX RS232RX 7 Serial Port SCIbRX 8 Serial Port SCIbTX 9 Serial Port Synchronous SCIcTX 10 Serial Port SCIbCK 11 Serial Port Synchronous SCIcCK 12 Serial Port Synchronous SCIcRX 13 Reserved 14 Reserved 15 Reserved 16 Reserved 17 Reserved 18 Reserved 19 Reserved 20 Reserved 21
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Table 5-5 below shows the Memory Expansion connections These connections support 5 to 3.3V level translation. JA3 Pin Generic Header Name Signal Name Pin Header Name Signal Name 1 A(0) A(0) 2 A(1) A(1) 3 A(2) A(2) 4 A(3) A(3) 5 A(4) A(4) 6 A(5) A(5) 7 A(6) A(6) 8 A(7) A(7) 9 A(8) A(8) 10 A(9) A(9) 11 A(10) A(10) 12 A(11) A(11) 13 A(12) A(12) 14 A(13) A(13) 15 A(14) A(14) 16 A(15) A(15) 17 D(0) D(0) 18 D(1) D(1) 19 D(2) D(2) 20
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Chapter 6.Code Development RSKs with appropriate connections will include suitable sample software to drive the interfaces on this board. 17
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Chapter 7.Additional Information For details on how to use High-performance Embedded Workshop (HEW), refer to the HEW manual available on the CD or from the web site. Online technical support and information is available at: http://www.renesas.com/renesas_starter_kits Technical Contact Details America: techsupport.rta@renesas.com Europe: tools.support.eu@renesas.com Japan: csc@renesas.com General information on Renesas Microcontrollers can be found on the Renesas website at: http://w
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Renesas Starter Kit Ethernet & USB Application Board User's Manual Publication Date Rev.2.00 17.Jan.2008 Published by: Renesas Technology Europe Ltd. Duke’s Meadow, Millboard Road, Bourne End Buckinghamshire SL8 5FH, United Kingdom ©2007 Renesas Technology Europe and Renesas Solutions Corp., All Rights Reserved.
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Renesas Starter Ethernet & USB Application Board User's Manual Renesas Technology Europe Ltd. Duke’s Meadow, Millboard Road, Bourne End Buckinghamshire SL8 5FH, United Kingdom
