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REJ10J1351-0101
SH7619 CPU Board
M3A-HS19
32
User's Manual
Renesas 32-Bit RISC Microcomputers
TM
SuperH RISC engine Family/SH7619 Group
Rev. 1.01
Issued : Oct 28, 2008
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Notes regarding these materials 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this do
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Table of Contents Chapter1 Overview ..............................................................................................................................1-1 1.1 Overview .................................................................................................................................................................... 1-2 1.2 Configuration................................................................................................................................
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3.2.2 Features of Switches and LEDs ...................................................................................................................... 3-18 3.3 Dimensions............................................................................................................................................................... 3-20 Appendix..............................................................................................................................................A-1
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Chapter1 Overview Chapter1 Overview 1-1
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Overview 1 1.1 Overview 1.1 Overview The M3A-HS19 is a CPU board designed to evaluate the feature and performance of the SH7619 Group of Renesas Technology original MCU, as well as developing and evaluating the application software for the MCUs. SH7619 data bus, address bus and on-chip peripheral pins are all connected to expansion connectors and appropriate connectors to allow for the timing evaluation with peripherals using measurement instruments, and the development of the optional
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Overview 1 1.3 External Specification 1.3 External Specifications Table 1.3.1 lists external specifications. Table 1.3.1 External Specifications No. Items Description 1 CPU SH7619 • Input (XIN) clock: 15.625 MHz • Bus clock: 62.5 MHz at maximum • CPU clock: 125 MHz at maximum 2 Memories • SDRAM (16-bit data bus) • EDS1216AATA-75E: 1 (16 MB) • Flash memory (16-bit data bus) • S29GL032A90TFIR4: 1 (4 MB) • EEPROM (Serial) • S93C76AFT-V-G: 1 (8 KB, 512 x 16) 3 Connectors • Expan
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Overview 1 1.4 1.4 Appearance Figure 1.4.1 shows the appearance of the M3A-HS19. Figure 1.4.1 M3A-HS19 Appearance Rev.1.01 Oct 28, 2008 1-4 REJ10J1351-0101
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Overview 1 1.5 M3A-HS19 Block Diagram 1.5 M3A-HS19 Block Diagrams Figure 1.5.1 shows the system block diagram. Serial port connector H-UDI (14-pin) (RS-232C x 2, RS-422 x 1) 16-bit Expansion connector SCIF HIF H-UDI /SCI (HIF bus) GPIO/ LAN Other EtherC SH7619 Peripheral connector Functions BSC Expansion connector (CPU bus) 16-bit 16-bit 16-bit SDRAM Flash Memory Bus switch SDRAM (16MB) (4MB) (16MB) (4MB) SH7619 CPU Board M3A-HS19 PCMCIA connector Figure 1.5.1 System Block Diagram
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Overview 1 1.6 M3A-HS19 Board Overview 1.6 M3A-HS19 Board Overview Figure 1.6.1 shows the M3A-HS19 board overview. Top view of the component side SW1 U7,U8,U9 Power switch Bus switch LED5 U5 Power LED PCMCIA power control IC LED1-4 J7 User LED Power connector J6 JP9 H-UDI connector Power switching (14-pin) jumper U6 J14 RS-232C AC adaptor jack driver J2 U12, U16 RS-232C 3.3V/1.8V serial connector regulator IC X3 25MHz oscillator X1 U1 15.625MHz oscillator SH7619 J5 RJ-45 SW2 LAN conn
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Overview 1 1.6 M3A-HS19 Board Overview Table 1.6.1 lists major components mounted on the M3A-HS19 Table 1.6.1 Major Components Remarks Recommended Optional Parts Part Name (By manufacturer) (By manufacturer) Number U1 CPU R4S76190W125BGV (Renesas) U2 Flash memory S29GL032A90TFIR4 (Spansion) U3 SDRAM EDS1216AATA-75E (Elpida) U4 EEPROM S93C76AFT-V-G (SII) U5 PCMCIA power control IC LTC1470CS8#PBF (Linear) U6 RS-232C driver SP3222ECY (Sipex) U7,U8,U9 Bus switch SN74CBTLV1
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Overview 1 1.7 M3A-HS19 Memory Mapping 1.7 M3A-HS19 Memory Mapping Area 0 bus width: (Default) MD3 = 0 •••16-bit Data alignment: (SW4-1) MD5 = 0(ON) •••Big endian MD5 = 1(OFF) •••Little endian Figure 1.7.1 show the memory mapping examples of the SH7619 on the M3A-HS19. Logical Address [31~29] Area Cacheable/Non-cacheable 000~011 P0 Cacheable 100~ P1 Cacheable 101~ P2 Non cacheable 110~ P3 Cacheable 111~ P4 Non-cacheable (on-chip I/O) etc. (P0 and shadow area (P1, P2, P3)
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Overview 1 1.8 Absolute Maximum Ratings 1.8 Absolute Maximum Ratings Table 1.8.1 lists the absolute maximum ratings. Table 1.8.1 Absolute Maximum Ratings Symbol Parameter Value Remarks 5 V system power supply voltage Relative to VSS VCC -0.3 to 6.0 V 3.3 V system power supply voltage Relative to VSS 3VCC -0.3 to 3.8 V system power supply voltage Relative to VSS 1.8VCC 1.8 V -0.3 to 2.1 V Operating temperature -5 to 55°C No condensation, no corrosion gas allowed. Topr Storag
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Overview 1 1.8 Absolute Maximum Ratings This page intentionally left blank Rev.1.01 Oct 28, 2008 1-10 REJ10J1351-0101
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Chapter2Features and Specifications Chapter2 Features and Specifications 2-1
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Features and Specifications 2 2.1 Features 2.1 Features Table 2.1.1 lists the functional modules. Table 2.1.1 Functional Modules Section Features Description 2.2 CPU SH7619, clock mode 1 • Input (XIN) clock: 15.625 MHz • Bus clock: 62.5 MHz, max. • CPU clock: 125 MHz, max. 2.3 Memories • U Memory (CPU) • 16-KB memory • Flash Memory • S29GL032A90TFIR4: 1 (4 MB) • SDRAM • EDS1216AATA-75E: 1 (16 MB) • EEPROM • S-93C76AFT-V-G: 1 (8 KB, 512 x 16) 2.4 Serial Port Interface Con
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Features and Specifications 2 2.2 CPU 2.2 CPU 2.2.1 SH7619 The M3A-HS19 CPU board includes the SH7619, the 32-bit RISC MCU operates with a maximum frequency of 125 MHz. The SH7619 is equipped with an Ethernet controller that includes an IEEE802.3u compliant Media Access Controller and a Physical Layer Transceiver. Moreover, the SH7619 has both a 16-KB U memory (RAM) and a 16-KB instruction/data unified cache memory. These on-chip modules enable the SH7619 to be used in a wide range of
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Features and Specifications 2 2.3 Memory 2.3 Memory The M3A-HS19 includes the SH7619 on-chip U memory, an external flash memory, external SDRAM and EEPROM. Details are described below (Except the PC card). 2.3.1 SH7619 U Memory and Cache Memory The SH7619 has a 16-KB (RAM) U memory module (address: H’E55FC000~H’E55FFFFF) and a 16-KB instruction/data-unified cache memory. 2.3.2 Flash Memory S29GL032A90TFIR4 (Standard component) The M3A-HS19 comes standard with a flash memory li
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Features and Specifications 2 2.3.2 Flash Memory S29GL032A90TFIR4 (Standard component) Table 2.3.2 Setting Example of Bus State Controller (Flash Memory Write and Read) User Area Applicable Device Settings for Bus State Controller CS0 S29GL032A90TFIR4 CS0 Space Bus Control Register: CS0BCR Initial value: H'36DB 0400 (MD3 = "L") Recommended value: H'1000 0400 • Idle Cycles between Write-Read Cycles and Write-Write Cycles IWW[1:0] = B'01: 1 idle cycle inserted • Data bus width BSZ[1:0
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Features and Specifications 2 2.3.3 External Synchronous DRAM 2.3.3 External Synchronous DRAM (SDRAM) The M3A-HS19 is provided with a 16-MB synchronous DRAM (SDRAM) as an external main memory. The SDRAM is controlled by the SH7619 on-chip bus state controller. The SDRAM is accessed in 16-bit bus. Table 2.3.3 lists SDRAM specifications used on the M3A-HS19, and Figure 2.3.3 shows its block diagram. Table 2.3.3 SDRAM Specifications Items Description Part Number EDS1216AATA-75E Confi
