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DSCLP/SSCLP-200/300
Two and One Channel RS-422/485
Low Profile Asynchronous
Communications Adapter
for PCI bus
User's Manual
QUATECH, INC. TEL: (330) 655-9000
5675 Hudson Industrial Parkway FAX: (330) 655-9010
Hudson, Ohio 44236 http://www.quatech.com
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WARRANTY INFORMATION Quatech, Inc. warrants the DSCLP-200/300 or SSCLP-200/300 to be free of defects for five (5) years from the date of purchase. Quatech, Inc. will repair or replace any board that fails to perform under normal operating conditions and in accordance with the procedures outlined in this document during the warranty period. Any damage that results from improper installation, operation, or general misuse voids all warranty rights. Please complete the following information
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2006 Quatech, Inc. NOTICE The information contained in this document cannot be reproduced in any form without the written consent of Quatech, Inc. Likewise, any software programs that might accompany this document can be used only in accordance with any license agreement(s) between the purchaser and Quatech, Inc. Quatech, Inc. reserves the right to change this documentation or the product to which it refers at any time and without notice. The authors have taken due care in the preparation of
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Declaration of Conformity Manufacturer's Name: Quatech Inc. Manufacturer's Address: 5675 Hudson Industrial Parkway Hudson, Ohio 44236 (USA) Application of Council Directive: 89/336/EEC Standards to which Conformity is Declared: * EN50081-1 (EN55022, EN60555-2, EN60555-3) * EN50082-1 (IEC 801-2, IEC 801-3, & IEC 801-4) Type of Equipment: Information Technology Equipment Equipment Class: Commercial, Residential, & Light Industrial Product Name: PCI Two Port or One Port Serial Co
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Table of Contents 1 General Information .............................. 8 2 Hardware Configuration ......................... 9 2.1 RS-422 or RS-485 Signal Line Termination ........... 9 2.2 Signal Connections ................................. 10 2.3 Full-duplex/Half-duplex Operation .................. 10 2.3.1 CTS0_SEL, CTS1_SEL (J10, 17) ................. 12 2.3.2 AUX0_SEL1,0, AUX1_SEL1,0 (J12, 11, 19, 18) ... 12 2.3.3 RCLK0_SEL, RCLK1_SEL (J13, 20) ............ 12 2.3.4 TGL0_SEL1,0, TGL1_SEL
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6.1 OS/2 ............................................... 35 6.2 DOS and other operating systems ................... 35 6.2.1 QTPCI.EXE ..................................... 36 7 External Connections ............................ 38 7.1 RTS/cts Handshake ................................. 39 7.2 RCLK .............................................. 39 7.3 TCLK .............................................. 40 7.4 AUXIN/AUXOUT Loopback ........................ 40 7.5 Half-Duplex/Full-Duplex/Auto-Toggl
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DSCLP/SSCLP-200/300 User's Manual 7
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1 General Information The Quatech, Inc. DSCLP-200/300 (two-port) and SSCLP-200/300 (one-port) provide RS-422 or RS-485 asynchronous serial communication interfaces for IBM-compatible personal computer systems using the PCI expansion bus. For general purposes, this manual usually makes reference only to the DSCLP-200/300. All information pertains equally to the SSCLP-200/300, with the exception that with the SSCLP there is just one port instead of two. The DSCLP-200/300 uses Quatech's new Enha
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2 Hardware Configuration The DSCLP-200/300 is automatically configured at boot time by the computer's BIOS or operating system. There are no required switches or jumpers to set for installation. This chapter lists a number of optional jumper settings that control various hardware features. Jumpers J1-J4, located in a column near the D-type connector (D-25 for DSCLP, D-9 for SSCLP), control the RS-422 or RS-485 signal line termination. Jumpers J5-J8, located in a column just to the right of
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2.2 Signal Connections The DSCLP-200/300 provides each of two serial ports with four differential signal pairs: TxD, RxD, AUXOUT, and AUXIN. TxD and RxD are always present at the connector. The AUXOUT and AUXIN signals can be used to support RTS/CTS handshaking, external clocking, or external signal loopback. The factory default configuration, as shown in Figure 2, is a loopback of AUXOUT to AUXIN at the connector, with RTS and CTS looped back on the board. There is an extensive discussion o
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Jumpers J10-J23 define the options for this card: SPAD J2 J3 X8 J4 X4 X2 J5 J10 CTS0_SEL J11 AUX0_SEL0 AUX0_SEL1 J12 J13 RCLK0_SEL J14 TGL0_SEL0 TGL0_SEL1 J15 J16 RXEN0_SEL J17 CTS1_SEL AUX1_SEL0 J18 J19 AUX1_SEL1 RCLK1_SEL J20 TGL1_SEL0 J21 J22 TGL1_SEL1 J23 RXEN1_SEL Figure 2 - Right Card Edge Jumpers DSCLP/SSCLP-200/300 User's Manual 11
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2.3.1 CTS0_SEL, CTS1_SEL (J10, 17) With NO jumpers on J10 or J17 the mode selection is CTS=AUXIN. With Jumpers installed the mode selection is CTS=RTS. 2.3.2 AUX0_SEL1,0, AUX1_SEL1,0 (J12, 11, 19, 18) With NO jumpers on J12 or J19 the mode selection is AUXOUT=RTS. With Jumpers installed on J12 or J19 and NO jumpers installed on J11 or J18, the mode selection is AUXOUT=TCLK. With Jumpers installed on J12, J11 or J19, J18, the mode selection is AUXOUT=AUXIN. 2.3.3 RCLK0_SEL, RCLK1_SEL (J13, 20
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2.4 Clock Rate and Optional Registers Figure 3 shows the jumper configuration as shipped from the factory, with two spare jumpers applied in neutral positions. Remove one or both and apply as shown in following subsections to set optional features. SPAD J2 J3 X8 X4 J4 J5 X2 Figure 3 --- Factory default clock rate and options settings 2.4.1 Enable Scratchpad Register (SPAD, J2) In the default configuration (see page 11), an Interrupt Status Register and an Options Register replace the scratchpad
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The factory default is none of these jumpers applied, which allows for software control of the clock multiplier via the Options Register. The Options Register powerup default is for a standard times-1 clock of 1.8432 MHz for compatibility with standard serial ports. Figure 5 --- Clock multiplier jumper options J2 J3 SPAD X8 X4 J4 J5 X2 factory default SPAD J2 J3 X8 X4 J4 J5 X2 X8 mode J2 J3 X8 SPAD J4 X4 X2 J5 X4 mode J2 J3 SPAD X8 X4 J4 J5 X2 X2 mode DSCLP/SSCLP-200/300 User's Manual 14
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3 Hardware Installation 1. Turn off the power of the computer system in which the DSCLP-200/300 is to be installed. 2. Remove the system cover according to the instructions provided by the computer manufacturer. 3. Make any desired optional jumper setting changes. 4. Install the DSCLP-200/300 in any empty PCI expansion slot. The board should be secured by installing the Option Retaining Bracket (ORB) screw. 5. Replace the system cover according to the instructions provided by the computer ma
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4 Address Map and Special Registers This chapter explains how the two UARTs and special registers are addressed, as well as the layout of those registers. This material will be of interest to programmers writing driver software for the DSCLP-200/300. 4.1 Base Address and Interrupt Level (IRQ) The base address and IRQ used by the DSCLP-200/300 are determined by the BIOS or operating system. Each serial port uses 8 consecutive I/O locations. The two ports reside in a single block of I/O space in
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4.2 Enabling the Special Registers The DSCLP-200/300 contains two unique registers, an Interrupt Status Register and an Options Register. These registers are enabled when the SPAD jumper (J13) is removed (factory default). They replace the UART Scratchpad Register on accesses to register address 7. The Interrupt Status Register and Options Register are accessed through the scratchpad location of any UART. The DLAB bit of the UART (Line Control Register, bit 7) is used to select between the t
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4.4 Quatech Modem Control Register The Quatech Modem Control Register can be used to set up each port. To access the QMCR write a 0xBF to the LCR (base + 3) and a 0x10 to the Options Register (base+7). This will allow the user read/write access to the QMCR. The QMCR of the entire DSCLP-200/300 is shown in Figure 9a. Bit Description 7 (MSB) 0 (always 0) 6 0 (always 0) 5 0 - RXEN=1 1 - RXEN=!TXEN 4 0 - Bits 2 and 3 are used 1 - RCLK=TCLK,CTS=RTS, AUXOUT=AUXIN 3 0 - RCLK=TCLK,CTS=AUXIN 1 - RCL
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4.5 Options Register The Options Register allows software to identify the DSCLP-200/300 as a Quatech Enhanced Serial Adapter. It also allows software to set the UART clock rate multiplier. Figure 10 shows the structure of the Options Register. The powerup default of the Options Register is all bits zero. Bit Name Description 7 (MSB) ID1 ID bit 1 6 ID0 ID bit 0 5 - (reserved, 0) 4 - (reserved, 0) 3 - (reserved, 0) 2 - (reserved, 0) 1 RR1 Clock rate multiplier bit 1 0 RR0 Clock rate multiplier b
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4.5.2 Clock Rate Multiplier A standard serial port operates at a clock speed of 1.8432 MHz. In order to achieve higher data rates, Quatech Enhanced Serial Adapters can operate at two, four, or eight times this standard clock speed. This is controlled by the clock rate multiplier bits in the Options Register. Software can determine the UART clock frequency by reading the clock rate multiplier bits RR1 and RR0 in the Options Register as shown in Figure 12. RR1 and RR0 can be set by writing to th
