Resumen del contenido incluido en la página 1
PCI-DIO96
DIGITAL INPUT/OUTPUT
User’s Manual
Revision 2
November, 2000
Resumen del contenido incluido en la página 2
TABLE OF CONTENTS 1 INTRODUCTION .............................................. 1 2 INSTALLATION ............................................... 2 3 I/O CONNECTIONS ........................................... 2 3.1 CABLES AND SCREW TERMINAL BOARDS ............. 2 3.2 CONNECTOR DIAGRAM .................................. 3 3.3 SIGNAL CONNECTION CONSIDERATIONS .............. 6 3.4 CIO-ERB24 & SSR-RACK24 CONNECTIONS .............. 7 4 SOFTWARE .................................................... 8 4
Resumen del contenido incluido en la página 3
This page is blank.
Resumen del contenido incluido en la página 4
1 INTRODUCTION The PCI-DIO96 is a 96-bit line digital I/O board. The board provides the 96 bits in four 24-bit groups. Each group provides an 8-bit port A and port B, as well as an 8-bit port C that can be split into independent 4-bit port C-HI and a 4-bit port C-LO. See Figure 1-1 below. On power up and reset, all I/O bits are set to input mode. If you are using the board to control items that must be OFF on reset, you will need to install pull-down resistors. Provisions have been made on the
Resumen del contenido incluido en la página 5
2 INSTALLATION The PCI-DIO96 boards are completely plug-and-play. There are no switches or jumpers on the board. All board addresses are set by your computer’s plug-and-play software. InstaCal is the installation, calibration and test software supplied with your data acquisition / IO hardware. Refer to the Extended Software Installation Manual to install InstaCal. If you need it, there is some on-line help in the InstaCal program. Owners of the Universal Library should read the manual and exami
Resumen del contenido incluido en la página 6
3.2 CONNECTOR DIAGRAM The PCI-DIO96 I/O connector is a 100-pin type connector accessible from the rear of the PC at the expansion backplate See Figure 3-1 below for the board pin out. Port A7 B 1 51 Port A7 D Port A6 B 2 52 Port A6 D Port A5 B 3 53 Port A5 D Port A4 B 4 54 Port A4 D Port A3 B 5 55 Port A3 D Port A2 B 6 56 Port A2 D Port A1 B 7 57 Port A1 D 58 Port A0 D Port A0 B 8 Port B7 B 9 59 Port B7 D Port B6 B 10 60 Port B6 D Port B5 B 11 61 Port B5 D Port B4 B 12 62 Port B4 D DIO Port B3
Resumen del contenido incluido en la página 7
BOARD’S C100FF-xx 100-PIN I/O CABLE CONNECTOR I/O PINS 1 TO 50 SIGNAL CONDITIONING or 50-PIN SCREW TERMINAL BOARD. I/O PINS 51 TO 100 SIGNAL CONDITIONING OR 50-PIN SCREW TERMINAL BOARD Figure 3-2. Cable C100FF-xx Configuration 4
Resumen del contenido incluido en la página 8
51 Port A7 D 52 Port A6 D 53 Port A5 D 54 Port A4 D 55 Port A3 D 56 Port A2 D 57 Port A1 D 58 Port A0 D 59 Port B7 D 60 Port B6 D Port A6 D 2 1 Port A7 D 61 Port B5 D Port A4 D 4 3 Port A5 D 62 Port B4 D Port A2 D 6 5 Port A3 D 63 Port B3 D Port A0 D 8 7 Port A1 D 64 Port B2 D Port B6 D 10 9 Port B7 D 11 Port B5 D DIO 65 Port B1 D Port B4 D 12 DIO 13 Port B3 D 66 Port B0 D Port B2 D 14 Group 3 Group 3 67 Port C7 D Port B0 D 16 15 Port B1 D 68 Port C6 D Port C6 D 18 17 Port C7 D 69 Port C5 D Port
Resumen del contenido incluido en la página 9
3.3 SIGNAL CONNECTION CONSIDERATIONS All the digital inputs on the PCI-DIO96 are 8255 CMOS TTL. The PCI-DIO96 output signals are 8255 CMOS. OMEGA Engineering Inc. offers a wide variety of digital signal conditioning products that provide an ideal interface between high voltage and/or high current signals and the PCI-DIO96. If you need control or monitor non-TTL level signals with your board, please refer to our catalog or our web site for the following products: CIO-ERB series, electromechan
Resumen del contenido incluido en la página 10
3.4 CIO-ERB24 & SSR-RACK24 CONNECTIONS PCI-DIO96 boards provide digital I/O in two major groups of 48 bits each (96 total, but each side of the C100FF-xx cable provides 48 bits). However, many popular relay and SSR boards provide only 24-bits of I/O. The CIO-ERB24 and SSR-RACK24 each implements a connector scheme where all 96 bits of the PCI-DIO96 board may be used to control relays and/or SSRs. This configuration is shown in Figure 3-4 below. The 24-bits of digital I/O on PCI-DIO96 connector pi
Resumen del contenido incluido en la página 11
4 SOFTWARE We highly recommend that users take advantage of our Universal Library package's easy-to-use programming interfaces. However, if you are an experienced programmer, and wish to read and write directly to the board, we have provided a detailed register map in the next chapter. 4.1 UNIVERSAL LIBRARY The Universal Library provides complete access to the PCI-DIO96 functions from a range of programming languages. If you are planning to write programs, or would like to run the example progra
Resumen del contenido incluido en la página 12
5 REGISTER MAPS The PCI Controller, a PLX-9052, has four configuration, control, and status registers (Table 5-1). They are described in the following section. Table 5-1. I/O Region Register Operations I/O Region Function Operations BADR0 PCI memory-mapped configuration 32-bit double word registers BADR1 PCI I/O-mapped config. registers 32-bit double word BADR2 N/A N/A BADR3 Digital I/O registers 8-bit byte 5.1 BADR0 BADR0 is reserved for the PLX-9052 configuration registers. There is no reason
Resumen del contenido incluido en la página 13
INTE Interrupt enable (local): 0 = disabled, 1 = enabled (default) INTPOL Interrupt polarity: 0 = active low (default), 1 = active high INT Interrupt status: 0 = interrupt not active, 1 = interrupt active PCINT PCI interrupt enable: 0 = disabled (default), 1 = enabled LEVEL/EDGE Interrupt trigger control: 0 = level triggered mode (default), 1 = edge triggered mode INTCLR Interrupt clear (edge triggered mode only): 0 = N/A, 1 = clear interrupt ISAMD ISA mode enable control (must be set to 1) 0
Resumen del contenido incluido en la página 14
5.4 BADR3 BADR3 is an 8-bit data bus for reading, writing and control of the individual 82C55 chips and the 82C54. Refer to Table 5-2 for register offsets. Table 5-2. BADR3 Registers REGISTER READ FUNCTION WRITE FUNCTION BADR3 + 0 Group 0 Port A Data Group 0 Port A Data BADR3 + 1 Group 0 Port B Data Group 0 Port B Data BADR3 + 2 Group 0 Port C Data Group 0 Port Data BADR3 + 3 Group 0 Configure Group 0 Configure BADR3 + 4 Group 1 Port A Data Group 1 Port A Data BADR3 + 5 Group 1 Port B Data Grou
Resumen del contenido incluido en la página 15
GROUP 0, PORT B DATA BADR3 + 1 READ/WRITE 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 GROUP 0, PORT C DATA BADR3 + 2 READ/WRITE 7 6 5 4 3 2 1 0 C8 C7 C6 C5 C4 C3 C2 C1 CH4 CH3 CH2 CH1 CL4 CL3 CL2 CL1 GROUP 0 CONFIGURE BADR3 + 3 READ/WRITE 7 6 5 4 3 2 1 0 MS M3 M2 A CH M1 B CL This register is used to configure the Group 0 ports as either input or output, and configures the operating mode to mode 0, 1 or 2. The following describes configuration for mode 0. See the Intel or Harris 8255 data sheets
Resumen del contenido incluido en la página 16
Table 5-3. DIO Port Configurations/Per Group Programming Codes Values D4 D3 D1 D0 Hex Dec A B CU CL 0 0 0 0 80 128 OUT OUT OUT OUT 0 0 0 1 81 129 OUT OUT OUT IN 0 0 1 0 82 130 OUT IN OUT OUT 0 0 1 1 83 131 OUT IN OUT IN 0 1 0 0 88 136 OUT OUT IN OUT 0 1 0 1 89 137 OUT OUT IN IN 0 1 1 0 8A 138 OUT IN IN OUT 0 1 1 1 8B 139 OUT IN IN IN 1 0 0 0 90 144 IN OUT OUT OUT 1 0 0 1 91 145 IN OUT OUT IN 1 0 1 0 92 146 IN IN OUT OUT 1 0 1 1 93 147 IN IN OUT IN 1 1 0 0 98 152 IN OUT IN OUT 1 1 0 1 99 153 IN O
Resumen del contenido incluido en la página 17
GROUP 1 CONFIGURE BADR3 + 7 READ/WRITE 7 6 5 4 3 2 1 0 MS M3 M2 A CH M1 B CL 5.4.3 Group 2 8255 Configuration & Data GROUP 2, PORT A DATA BADR3 + 8 READ/WRITE 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 GROUP 2, PORT B DATA BADR3 + 9 READ/WRITE 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 GROUP 2, PORT C DATA BADR3 + A hex READ/WRITE 7 6 5 4 3 2 1 0 C8 C7 C6 C5 C4 C3 C2 C1 CH4 CH3 CH2 CH1 CL4 CL3 CL2 CL1 GROUP 2 CONFIGURE BADR3 + B hex READ/WRITE 7 6 5 4 3 2 1 0 MS M3 M2 A CH M1 B CL 5.4.4 Group 3 8255
Resumen del contenido incluido en la página 18
GROUP 3, PORT B DATA BADR3 + D hex READ/WRITE 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 GROUP 3, PORT C DATA BADR3 + E hex READ/WRITE 7 6 5 4 3 2 1 0 C8 C7 C6 C5 C4 C3 C2 C1 CH4 CH3 CH2 CH1 CL4 CL3 CL2 CL1 GROUP 3 CONFIGURE BADR3 + F hex READ/WRITE 7 6 5 4 3 2 1 0 MS M3 M2 A CH M1 B CL 5.4.5 8254 Configuration & Data COUNTER 1 DATA BADR3 + 10 hex READ/WRITE 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 The 82C54 counters 1 and 2 have been configured in hardware to produce a 32-bit counter for use in i
Resumen del contenido incluido en la página 19
COUNTER CONFIGURATION BADR3 + 13 hex READ/WRITE 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 This register is used to set the operating modes of each of the 82C54’s counters. Configure the counters by writing mode information to the Configure register, followed by the count information written to the specific counter (data) registers. Refer to the Celeritous 82C54 data sheets for more detailed information. 5.4.6 8255 Interrupt Source Configure BADR3 + 14 hex READ/WRITE 7 6 5 4 3 2 1 0 DIRQ1 DIRQ0 CI
Resumen del contenido incluido en la página 20
5.4.7 Counter Interrupt Source Configure BADR3 + 15 hex READ/WRITE 7 6 5 4 3 2 1 0 X X X X X INTEN CTRIR CTR1 INTEN Enables or disabled interrupts. 1 = enabled, 0 = disabled CTRIR Enables or disables the counters as an interrupt source. 1 = counters may generate interrupts. 0 = counters cannot generate interrupts. CTR1 Controls whether counter 2 is the interrupt source, or counter 1 is the interrupt source. When CTR1 is set to 1, the interrupt source is counter 2 and counter 1 acts as a pre
