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PD672X/30/32/33 — ZV Port
Implementation
Application Note
May 2001
As of May 2001, this document replaces the Basis Communications Corp. document AN-PD10.
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PD672X/30/32/33 — ZV Port Implementation Contents 1.0 Introduction ..................................................................................................................5 2.0 Overview ........................................................................................................................6 3.0 Zoomed Video (ZV)....................................................................................................6 4.0 A Typical ZV Port Implementation ......................
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PD672X/30/32/33 — ZV Port Implementation 4 Application Note
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PD672X/30/32/33 — ZV Port Implementation 1.0 Introduction The PD6710, PD6722, and PD6729 are single-chip PCMCIA interface controllers capable of controlling one or two PCMCIA or compact Flash sockets, respectively. They are designed for use in embedded applications and notebook systems where reduced form factor and low power consumption are critical design objectives. Current typical application examples include: Routers Integrated access devices Access network servers DSLAMs PBXs
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PD672X/30/32/33 — ZV Port Implementation 2.0 Overview This application note discusses system design considerations associated with the implementation of the ZV (Zoomed Video) Port when using the PD6722/’29/’30, or PD6832 controller devices. Intended to assist the system designer, this document highlights how various aspects of the PC Card relate to the ZV Port implementation. Since the ZV Port implementation overlaps PC Card, graphics, and audio technologies, consulting with appropriate appl
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PD672X/30/32/33 — ZV Port Implementation Note that ZV Port implementation is likely to vary depending on the platform; the Socket Services software must be customized to address these variances. Controlling the OE (output enable) inputs of the external buffers depends upon specific hardware design and software needs to be aware of specifics, such as the I/O Port addresses. When the PC Card Multimedia mode is used, Intel recommends that the ZV Port pins be connected as shown in Tables 1–3 for
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PD672X/30/32/33 — ZV Port Implementation A buffer circuit placed between the PC Card bus and the VGA video port reduces the trace length to lower the loading effect. The ZV Port standard requires that the length of the trace between the PC Card connector and the buffer (if used) must be less than two inches. Buffers are also needed to support ZV Port PC Cards in either socket. In a full implementation of the ZV Port, multiple PC Card slots can be used to implement the ZV Port. This implies t
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PD672X/30/32/33 — ZV Port Implementation 5.0 Dedicated Socket Approach to ZV Port Implementation Figure 2 shows a solution using the PD6722/’29/’30/’6832 Controller and the GD7XXX Super VGA controller to support a single dedicated ZV Port slot. This simple implementation does not require any external buffer or glue logic; the only limitation is that one socket must be dedicated to the ZV Port. Also, depending upon the audio controller used, a buffer may be required between the PC Card bus a
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PD672X/30/32/33 — ZV Port Implementation 6.0 Buffer Implementation for Audio DAC A buffer solution to isolate the audio controller when the socket is not configured in ZV Port mode is shown in Figure 3. This illustrates how to control the buffer enable; if the GD7XXX is used, then one of the GPO pins can control the buffer enable. Figure 3. Buffer Implementation for Audio DAC GD7XXX V-PORT PD6722 PD6729 PD6730 ZV PORT PC CARD PC CARD BUS PD6832 PD6833 OE BUFFER AUDIO 10 Application Note
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PD672X/30/32/33 — ZV Port Implementation 7.0 ZV Port Implementation for Socket A and B Figure 4 shows the ZV Port support for socket A and B. If using the GD7XXX, two of the GPO pins can control the buffer output enables. Since there is only one V-Port, a ZV Port PC Card can be inserted in either Socket A or Socket B. Figure 4. ZV Port Implementation for Socket A and B TVON VPCNTL GD7XXX GLUE LOGIC V-PORT 2 NAND GATES 1 INVERTER AUDIO OE OE BUFFER BUFFER SOCKET A Z R PD6722 PC CARD BUS A P ZV
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PD672X/30/32/33 — ZV Port Implementation Table 1. PC Card, ZV Port, and PD6722 Pin Assignment (Sheet 2 of 2) PC Card I/O in PC PC Card ZV Port Pin I/O in ZV PD6722S PD6722S Pin Card Comments Pin Name Port Mode ocket A ocket B Number Mode 19 A16 I UV2 O 41 103 Video data to ZV Port 20 A15 I UV4 O 43 105 Video data to ZV Port 21 A12 I UV6 O 45 107 Video data to ZV Port 22 A7 I SCLK I 47 109 Audio SCLK PCM signal 23 A6 I MCLK I 49 112 Audio MCLK PCM signal Tristated by Controller; no 24–25 A[5:4]
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PD672X/30/32/33 — ZV Port Implementation Table 2. PC Card, ZV Port, and PD6729 Pin Assignment (Sheet 2 of 2) PC Card I/O in PC PC Card ZV Port Pin I/O in ZV PD6729S PD6729S Pin Card Comments Pin Name Port Mode ocket A ocket B Number Mode 21 A12 I UV6 O 101 176 Video data to ZV Port 22 A7 I SCLK I 104 179 Audio SCLK PCM signal 23 A6 I MCLK I 106 181 Audio MCLK PCM signal Tristated by Controller; no 24–25 A[5:4] I RESERVED RFU 108, 110 183, 185 connection in PC Card 112, 114, 187,190, Used for a
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PD672X/30/32/33 — ZV Port Implementation Table 3. PC Card, ZV Port, and PD6730/’6832 Pin Assignment (Sheet 2 of 2) I/O in PC PD6730 or PD6730 or PC Card PC Card ZV Port Pin I/O in ZV Card PD6832 PD6832 Comments Pin No. Pin Name Port Mode Mode Socket A Socket B 23 A6 I MCLK I 103 178 Audio MCLK PCM signal Tristated by Controller; no 24–25 A[5:4] I RESERVED RFU 105, 107 181, 183 connection in PC Card ADDRESS 109,111, 185,187, 26–29 A[3:0] I I Used for accessing PC Card [3:0] 113,116 189, 191 3
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PD672X/30/32/33 — ZV Port Implementation 8.0 Layout Guidelines The VGA controller, the PC Card (PCMCIA) Controller, and the PC Card Sockets must be in close proximity to one another. This requirement is particularly important when the PD6832 or PD6833 device is used along with the ZV Port for Card bus implementation. According to tests conducted by PCMCIA ZV Port subcommittee, the stubs to the GD7548 device or any other VGA controller must be no longer than two inches. As shown in Figure 4 o
