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CY7C1246V18, CY7C1257V18
CY7C1248V18, CY7C1250V18
36-Mbit DDR-II+ SRAM 2-Word
Burst Architecture (2.0 Cycle Read Latency)
Features Functional Description
■ 36-Mbit density (4M x 8, 4M x 9, 2M x 18, 1M x 36) The CY7C1246V18, CY7C1257V18, CY7C1248V18, and
CY7C1250V18 are 1.8V Synchronous Pipelined SRAM
■ 300 MHz to 375 MHz clock for high bandwidth
equipped with DDR-II+ architecture. The DDR-II+ consists of an
SRAM core with advanced synchronous peripheral circuitry.
■ 2-Word burst for reducing add
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2M x 8 Array 2M x 9 Array 2M x 8 Array 2M x 9 Array CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 Logic Block Diagram (CY7C1246V18) Write Write 21 A (20:0) Reg Reg Address Register LD 8 K Output CLK K Logic R/W Gen. Control DOFF Read Data Reg. 16 CQ V 8 REF 8 Reg. Reg. CQ Control R/W 8 Logic DQ [7:0] 8 NWS [1:0] Reg. 8 QVLD Logic Block Diagram (CY7C1257V18) Write Write 21 A (20:0) Reg Reg Address Register LD 9 K Output CLK K Logic R/W Gen. Control DOFF Read Data Reg. 18 CQ V 9 REF 9 Reg. Reg
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512K x 36 Array 1M x 18 Array 1M x 18 Array 512K x 36 Array CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 Logic Block Diagram (CY7C1248V18) Write Write 20 A (19:0) Reg Reg Address Register LD 18 K Output CLK K Logic R/W Gen. Control DOFF Read Data Reg. 36 CQ V 18 REF 18 Reg. Reg. CQ Control R/W Logic DQ [17:0] 18 BWS 18 [1:0] Reg. 18 QVLD Logic Block Diagram (CY7C1250V18) Write Write 19 A (18:0) Reg Reg Address Register LD 36 K Output CLK K Logic R/W Gen. Control DOFF Read Data Reg. 72 CQ V
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CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 Pin Configurations 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1246V18 (4M x 8) 1 23 4 5 6 7 89 10 11 NC/72M A NC/144M AA CQ A CQ R/W NWS K LD 1 NC NC NC A NC/288M K A NC NC DQ3 B NWS 0 NC NC NC AAA NC NC NC C V V SS SS NC NC NC V V V V V NC NC NC D SS SS SS SS SS NC NC DQ4 V V V V V NC NC DQ2 E DDQ SS SS DDQ SS F NC NC NC V V V V V NC NC NC DDQ DD SS DD DDQ G NC NC DQ5 V V V V V NC NC NC DDQ DD SS DD DDQ H V V V V V V V V V ZQ DOFF REF DDQ DDQ
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CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 Pin Configurations (continued) 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1248V18 (2M x 18) 1 23 4 5 6 7 89 10 11 NC/72M A NC/144M AA CQ A CQ R/W BWS K LD 1 NC DQ9 NC A NC/288M K A NC NC DQ8 B BWS 0 C NC NC NC V ANC A V NC DQ7 NC SS SS NC NC DQ10 V V V V V NC NC NC D SS SS SS SS SS NC NC DQ11 V V V V V NC NC DQ6 E DDQ SS SS SS DDQ F NC DQ12 NC V V V V V NC NC DQ5 DDQ DD SS DD DDQ G NC NC DQ13 V V V V V NC NC NC DDQ DD SS DD DDQ H V V V V V V V
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CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 Pin Definitions Pin Name IO Pin Description Data Input/Output Signals. Inputs are sampled on the rising edge of K and K clocks during DQ Input/Output- [x:0] valid write operations. These pins drive out the requested data during a read operation. Valid Synchronous data is driven out on the rising edge of both the K and K clocks during read operations. When read access is deselected, Q are automatically tri-stated. [x:0] CY7C1246V18 − DQ [7:0] C
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CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 Pin Definitions (continued) Pin Name IO Pin Description ZQ Input Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus impedance. CQ, CQ, and Q output impedance are set to 0.2 x RQ, where RQ is a [x:0] resistor connected between ZQ and ground. Alternatively, this pin can be connected directly to V , which enables the minimum impedance mode. This pin cannot be connected directly to DDQ GND or le
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CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 When write access is deselected, the device ignores all inputs Functional Overview after the pending write operations are completed. The CY7C1246V18, CY7C1257V18, CY7C1248V18, and Byte Write Operations CY7C1250V18 are synchronous pipelined Burst SRAMs equipped with a DDR interface. Byte write operations are supported by the CY7C1248V18. A write operation is initiated as described in the Write Operations Accesses for both ports are initiated on
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CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 be disabled by applying ground to the DOFF pin. When the DLL Valid Data Indicator (QVLD) is turned off, the device behaves in DDR-I mode (with 1.0 cycle QVLD is provided on the DDR-II+ to simplify data capture on high latency and a longer access time). For more information, refer to speed systems. The QVLD is generated by the DDR-II+ device the application note, DLL Considerations in along with data output. This signal is also edge aligned with t
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CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 Write Cycle Descriptions [2, 8] The write cycle descriptions table for CY7C1246V18 and CY7C1248V18 follows. BWS / BWS / 0 1 K Comments K NWS NWS 0 1 L L L–H – During the data portion of a write sequence: CY7C1246V18 − both nibbles (D ) are written into the device. [7:0] CY7C1248V18 − both bytes (D ) are written into the device. [17:0] L L – L-H During the data portion of a write sequence: CY7C1246V18 − both nibbles (D ) are written into the de
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CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 Write Cycle Descriptions [2, 8] The write cycle descriptions table for CY7C1250V18 follows. BWS BWS BWS BWS K K Comments 0 1 2 3 LLLL L-H – During the data portion of a write sequence, all four bytes (D ) are written [35:0] into the device. LLLL – L-H During the data portion of a write sequence, all four bytes (D ) are written [35:0] into the device. L H H H L-H – During the data portion of a write sequence, only the lower byte (D ) is [8:
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CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 Instruction Register IEEE 1149.1 Serial Boundary Scan (JTAG) Three-bit instructions can be serially loaded into the instruction These SRAMs incorporate a serial boundary scan test access register. This register is loaded when it is placed between the TDI port (TAP) in the FBGA package. This part is fully compliant with and TDO pins as shown in “TAP Controller Block Diagram” on IEEE Standard #1149.1-2001. The TAP operates using JEDEC page 15. Upon
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CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 IDCODE PRELOAD places an initial data pattern at the latched parallel outputs of the boundary scan register cells before the selection The IDCODE instruction loads a vendor-specific, 32-bit code into of another boundary scan test operation. the instruction register. It also places the instruction register between the TDI and TDO pins and shifts the IDCODE out of the The shifting of data for the SAMPLE and PRELOAD phases can device when the TAP co
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CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 TAP Controller State Diagram [9] The state diagram for the TAP controller follows. TEST-LOGIC 1 RESET 0 1 1 1 TEST-LOGIC/ SELECT SELECT 0 IDLE DR-SCAN IR-SCAN 0 0 1 1 CAPTURE-DR CAPTURE-IR 0 0 SHIFT-DR 0 SHIFT-IR 0 1 1 1 1 EXIT1-DR EXIT1-IR 0 0 0 0 PAUSE-DR PAUSE-IR 1 1 0 0 EXIT2-DR EXIT2-IR 1 1 UPDATE-DR UPDATE-IR 1 1 0 0 Note 9. The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document Number: 001-06348 Rev. *D
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CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 TAP Controller Block Diagram 0 Bypass Register Selection Selection Circuitry Circuitry 2 1 0 TDO TDI Instruction Register 31 30 29 . . 2 1 0 Identification Register . . . . 2 1 0 108 Boundary Scan Register TCK TAP Controller TMS TAP Electrical Characteristics [10, 11, 12] Over the Operating Range Parameter Description Test Conditions Min Max Unit V Output HIGH Voltage I = −2.0 mA 1.4 V OH1 OH V Output HIGH Voltage I = −100 μA1.6 V OH2 OH V Out
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CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 TAP AC Switching Characteristics [13, 14] Over the Operating Range Parameter Description Min Max Unit t TCK Clock Cycle Time 50 ns TCYC t TCK Clock Frequency 20 MHz TF t TCK Clock HIGH 20 ns TH t TCK Clock LOW 20 ns TL Setup Times t TMS Setup to TCK Clock Rise 5 ns TMSS t TDI Setup to TCK Clock Rise 5 ns TDIS t Capture Setup to TCK Rise 5 ns CS Hold Times t TMS Hold after TCK Clock Rise 5 ns TMSH t TDI Hold after Clock Rise 5 ns TDIH t Capture H
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CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 Identification Register Definitions Value Instruction Description Field CY7C1246V18 CY7C1257V18 CY7C1248V18 CY7C1250V18 Revision 000 000 000 000 Version number. Number (31:29) Cypress Device 11010111100000111 11010111100001111 11010111100010111 11010111100100111 Defines the type ID (28:12) of SRAM. Cypress JEDEC 00000110100 00000110100 00000110100 00000110100 Enables unique ID (11:1) identification of SRAM vendor. ID Register 1 1 1 1 Indicat
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CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID 0 6R 28 10G 56 6A 84 1J 1 6P29 9G 57 5B85 2J 2 6N 30 11F 58 5A 86 3K 3 7P 31 11G 59 4A 87 3J 4 7N32 9F 60 5C88 2K 5 7R 33 10F 61 4B 89 1K 6 8R 34 11E 62 3A 90 2L 7 8P 35 10E 63 2A 91 3L 8 9R 36 10D 64 1A 92 1M 9 11P 37 9E 65 2B 93 1L 10 10P 38 10C 66 3B 94 3N 11 10N 39 11D 67 1C 95 3M 12 9P 40 9C 68 1B 96 1N 13 10M 41 9D 69 3D 97 2M 14 11N 42 11B 70 3C 98 3P 15 9M 43 11C
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CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 DLL Constraints Power Up Sequence in DDR-II+ SRAM DDR-II+ SRAMs must be powered up and initialized in a ■ DLL uses K clock as its synchronizing input. The input must predefined manner to prevent undefined operations. During have low phase jitter, which is specified as t . KC Var power up, when the DOFF is tied HIGH, the DLL is locked after ■ The DLL functions at frequencies down to 120 MHz. 2048 cycles of stable clock. ■ If the input clock is un
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CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 Current into Outputs (LOW)......................................... 20 mA Maximum Ratings Static Discharge Voltage (MIL-STD-883, M 3015).... >2001V Exceeding maximum ratings may impair the useful life of the Latch up Current..................................................... >200 mA device. These user guidelines are not tested. Storage Temperature ................................ –65°C to + 150°C Operating Range Ambient Temperature with Power
