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®
SUPER
SUPER P3TDDR
USER’S MANUAL
Revision 1.0a
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The information in this User’s Manual has been carefully reviewed and is believed to be accurate. The vendor assumes no responsibility for any inaccuracies that may be contained in this document, makes no commitment to update or to keep current the information in this manual, or to notify any person or organization of the updates. Please Note: For the most up-to-date version of this manual, please see our web site at < http://www.supermicro.com >. SUPERMICRO COMPUTER reserves the right to make
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Preface Preface About This Manual This manual is written for system integrators, PC technicians and knowledgeable PC users. It provides information for the installation and use of the SUPER P3TDDR motherboards. The SUPER P3TDDR supports single ® or dual Pentium III FCPGA 500 MHz-1.26 GHz+ processors, including low ® power Pentium III processors, at Front Side Bus speeds of 133, 100 and 66 MHz. Please refer to the support section of our web site (http:// www.supermicro.com/TechSupport.htm) fo
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SUPER P3TDDR User’s Manual Table of Contents About This Manual ...................................................................................................... iii Manual Organization ................................................................................................... iii Chapter 1: Introduction 1-1 Overview......................................................................................................... 1-1 Checklist .............................................
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Table of Contents Wake-On-Ring .........................................................................................2-10 Fan Headers........................................................................................... 2-11 Chassis Intrusion ....................................................................................2-11 2-7 Jumper Settings ............................................................................................ 2-12 Explanation of Jumpers ...................
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SUPER P3TDDR User’s Manual 4-9 Exit Setup ....................................................................................................... 4-25 Appendices: Appendix A: AwardBIOS POST Messages ......................................................... A-1 Appendix B: AwardBIOS POST Codes .................................................................B-1 Appendix C: AwardBIOS Beep Codes ..................................................................C-1 vi
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Chapter 1: Introduction Chapter 1 Introduction 1-1 Overview Checklist Congratulations on purchasing your computer motherboard from an ac- knowledged leader in the industry. Supermicro boards are designed with the utmost attention to detail to provide you with the highest standards in quality and performance. Please check that the following items have all been included with your P3TDDR motherboard. If anything listed here is damaged or missing, con- tact your retailer. One (1) Supermicro P3TDDD
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SUPER P3TDDR User's Manual Contacting Supermicro Headquarters Address: Super Micro Computer, Inc. 980 Rock Ave. San Jose, CA 95131 U.S.A. Tel: +1 (408) 503-8000 Fax: +1 (408) 503-8008 E-mail: marketing@supermicro.com (General Information) support@supermicro.com (Technical Support) Web site: www.supermicro.com Europe Address: Super Micro Computer B.V. Het Sterrenbeeld 28, 5215 ML, 's-Hertogenbosch, The Netherlands Tel: +31 (0) 73-6400390 Fax: +31 (0) 73-6416525 E-mail: sales@supermicro.nl (Genera
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Chapter 1: Introduction SUPER P3TDDR Figure 1-1. SUPER P3TDDR Image 1-3 Introduction
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SUPER P3TDDR User's Manual Figure 1-2. SUPER P3TDDR Layout (not drawn to scale) KB/ ATX POWER JPWAKE J6 CPU Fan 1 JF1 Overheat Fan Mouse J1 USB 0/1 370-pin FCPGA/ PPGA COM1 Processor CPU Fan 2 CPU 1 370-pin VGA FCPGA/ PPGA Processor VIA VT8653 LAN 1 CPU 2 LAN 2 ATI Chassis Rage XL Fan 2 Chassis JP10 JP3 Fan 1 PCI 1 JPL1 PCI 2 BIOS VIA PCI 3 VT8233 SUPER I/O JPL2 JP2 JP10 Adaptec BATTERY AIC-7899 SPKR JPA2 JPA1 JP8 1
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Chapter 1: Introduction P3TDDR Quick Reference Jumpers Description Default Setting JBT1 CMOS Clear Pins 1-2 (Normal) JPA1/2 SCSI Ch A/B Termination Open (Enabled) JPL1/2 LAN 1/2 Enable/Disable Closed (Enabled) JPWAKE Keyboard Wake-Up Pins 1-2 (Disabled) JP2 SCSI Enable/Disable Pins 1-2 (Enabled) JP3 VGA Enable/Disable Pins 1-2 (Enabled) JP6, JP7 Front Side Bus Speed Select (See page 2-12) JP8 Speaker Enable/Disable Pins 1-2 (Enabled) JP10 VGA IRQ Enable/Disable Pins 1-2 (Enabled) Connectors Desc
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SUPER P3TDDR User's Manual Pentium III FCPGA/PPGA CPUs 133/100/66 MHz Host Bus 266 MHz VT8653T Memory Bus Memory GCLK DDR Vlink 3D Graphics MCLK Controller Host North Clock Buffer AGP Bus 552BGA HCLK/PCLK Clock Generator SMBus PCI Slots Power Plane & Peripheral Control VT8233 PCI Bus Vlink ATA 33/66/100 ACPI Events MII/LAN 6x USB LPC LPC Figure 1-3. VIA 266T Chipset: System Block Diagram 1-6
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Chapter 1: Introduction Motherboard Features CPU TM ® • Single or dual Intel Pentium III FCPGA 500 MHz-1.26+ GHz proces- TM sors (including low power Pentium III processors) at Front Side (system) Bus speeds of 133/100/66 MHz Note: Please refer to the support section of our web site for a complete list of supported processors. You must use the server version of the processors mentioned above. Memory • Four DIMM sockets to support up to 4 GB PC1600 or PC2100 DDR-RAM Chipset • VIA Apollo Pro 266
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SUPER P3TDDR User's Manual ACPI/PC 98 Features ® • Microsoft OnNow • Real-time clock wake-up alarm • Main switch override mechanism • External modem ring-on Onboard I/O • AIC-7899 for dual channel Ultra160 SCSI • 2 IDE bus master interfaces support UDMA/100 • 1 floppy port interface (up to 2.88 MB) • 2 Fast UART 16550A compatible serial ports • 1 EPP (Enhanced Parallel Port) / ECP (Extended Capabilities Port) supported parallel (printer) port • PS/2 mouse and PS/2 keyboard ports • 1 infrared por
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Chapter 1: Introduction 1-2 Chipset Overview The VIA Apollo Pro 266T chipset is a high performance, cost-effective and energy-efficient chipset for the implementation of AGP/V-Link/PCI/LPC com- puter systems based on 64-bit, 370-pin Pentium III (66/100/133 MHz FSB) processors. VIA's Apollo Pro 266T chipset consists of two major components: the VT8653 V-Link Memory Host System controller (North Bridge) and the VT8233 V-Link Client PCI/LPC controller (South Bridge). The VT8653 Host System Control
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SUPER P3TDDR User's Manual 1-3 PC Health Monitoring This section describes the PC health monitoring features of the SUPER P3TDDR motherboard. Seven Onboard Voltage Monitors for the CPU Core, Chipset Voltage, +3.3V, ±±±±±5V and ±±±±±12V The onboard voltage monitor will scan these seven voltages continuously. If a voltage becomes unstable, the monitor will give a warning or send an error message to the screen. Users can adjust the voltage thresholds to define the sensitivity of the voltage monit
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Chapter 1: Introduction CPU Overheat LED and Control This feature is available when the user enables the CPU overheat warning function in the BIOS. This allows the user to define an overheat tempera- ture. When this temperature is exceeded, both the overheat fan and the warning LED are triggered. System Resource Alert This feature is available when used with Intel's LANDesk Client Manager (optional). It is used to notify the user of certain system events. For example, if the system is running
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SUPER P3TDDR User's Manual ages the Plug and Play BIOS data structures while providing a processor architecture-independent implementation that is compatible with both Win- dows 98, Windows NT and Windows 2000. You can check to see if ACPI has been properly installed by looking for it in the Device Manager, which is located in the Control Panel in Windows. Microsoft OnNow The OnNow design initiative is a comprehensive, system-wide approach to system and device power control. OnNow is a term
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Chapter 1: Introduction External Modem Ring-On Wake-up events can be triggered by a device such as the external modem ringing when the system is in the SoftOff state. Note that external modem ring-on can only be used with an ATX 2.01 (or above) compliant power supply. Wake-On-LAN (WOL) Wake-On-LAN is defined as the ability of a management application to power up a computer remotely that is powered off. Remote PC setup, updates and asset tracking can occur after-hours and on weekends so that dai
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SUPER P3TDDR User's Manual 1-6 Super I/O The functions of the disk drive adapter for the Super I/O chip include a floppy disk drive controller that is compatible with industry standard 82077/ 765, a data separator, write pre-compensation circuitry, decode logic, data rate selection, a clock generator, drive interface control logic and interrupt and DMA logic. The wide range of functions integrated onto the Super I/O greatly reduces the number of components required for interfacing with floppy d
