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Si5351A/B/C
2
I C-PROGRAMMABLE ANY-FREQUENCY CMOS CLOCK
GENERATOR + VCXO
Features
Generates up to 8 non-integer-related Glitchless frequency changes
10-MSOP
frequencies from 8 kHz to 160 MHz Separate voltage supply pins:
2
Core VDD: 2.5 or 3.3 V
I C user definable configuration
Output VDDO: 1.8, 2.5, or 3.3 V
Exact frequency synthesis at each output
Excellent PSRR eliminates external
(0 ppm error)
power supply filtering
Highly linear VCXO
Very low power consumption
Opti
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Si5351A/B/C 2 Preliminary Rev. 0.95
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Si5351A/B/C TABLE OF CONTENTS Section Page 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. Detailed Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3.1. Input Stage . . . . . . . . . . . . . . . . . . . . . . .
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Si5351A/B/C 1. Electrical Specifications Table 1. Recommended Operating Conditions Parameter Symbol Test Condition Min Typ Max Unit Ambient Temperature T –40 2585°C A 3.0 3.3 3.60 V Core Supply Voltage V DD 2.25 2.5 2.75 V 1.71 1.8 1.89 V Output Buffer Voltage V 2.25 2.5 2.75 V DDOx 3.0 3.3 3.60 V Notes:All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25 °
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Si5351A/B/C Table 3. AC Characteristics (V = 2.5 V ±10%, or 3.3 V ±10%, T = –40 to 85 °C) DD A Parameter Symbol Test Condition Min Typ Max Unit From V =V to valid DD DDmin Power-up Time T output clock, C =5pF, —1 10 ms RDY L f >1MHz CLKn From OEB pulled low to valid Output Enable Time T clock output, C =5pF, —— 10 µs OE L f >1MHz CLKn Output Phase Offset P — 333 — ps/step STEP Down spread –0.1 — –2.5 % Spread Spectrum Frequency SS DEV Deviation Center spread ±0.1 — ±1.5 % Spread Spectrum Modu
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Si5351A/B/C Table 5. Output Clock Characteristics (V = 2.5 V ±10%, or 3.3 V ±10%, T =–40 to 85 °C) DD A Parameter Symbol Test Condition Min Typ Max Units Frequency Range F 0.008 — 160 MHz CLK Load Capacitance C —5 15 pF L Measured at V /2, DD Duty Cycle DC 45 50 55 % f =50MHz CLK t 0.5 1 1.5 ns r 20%–80%, C =5pF, L Rise/Fall Time Drive Strength = 8 mA t 0.5 1 1.5 ns f Output High Voltage V V – 0.6 — — V OH DD C =5pF L Output Low Voltage V —— 0.6 V OL Period Jitter J — 35 100 ps pk-pk PER Measur
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Si5351A/B/C 2 1 Table 7. I C Specifications (SCL,SDA) Parameter Symbol Test Condition Standard Mode Fast Mode Unit 100 kbps 400 kbps Min Max Min Max LOW Level 0.3 x V 2 DDI2 V –0.5 –0.5 0.3xV V ILI2C DDI2C Input Voltage C HIGH Level 0.7 x V 2 DDI2 V 3.63 0.7xV 3.63 V IHI2C DDI2C Input Voltage C Hysteresis of Schmitt Trigger V —— 0.1 — V HYS Inputs 2 LOW Level V =2.5/3.3V 0 0.4 0 0.4 V DDI2C Output Voltage (open drain or 2 V OLI2C open collector) 2 V = 1.8 V — — 0 0.2 x V V DDI2C DDI2C at 3
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Si5351A/B/C 1 Table 9. Absolute Maximum Ratings Parameter Symbol Test Condition Value Unit DC Supply Voltage V –0.5 to 3.8 V DD_max V CLKIN, SCL, SDA –0.5 to 3.8 V IN_CLKIN Input Voltage V VC –0.5 to (VDD+0.3) V IN_VC V Pins XA, XB –0.5 to 1.3 V V IN_XA/B Junction Temperature T –55 to 150 °C J Soldering Temperature (Pb-free T 260 °C 2 PEAK profile) Soldering Temperature Time at T 20–40 Sec 2 P TPEAK (Pb-free profile) Notes: 1. Permanent device damage may occur if the absolute maximum ratings
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Si5351A/B/C 2. Detailed Block Diagrams VDD VDDO Si5351A 3-Output PLL MultiSynth R0 A CLK0 0 XA OSC PLL XB MultiSynth R1 CLK1 B 1 SDA 2 I C MultiSynth R2 CLK2 Interface 2 SCL GND 10-MSOP VDD Si5351A 8-Output VDDOA MultiSynth R0 PLL CLK0 0 A XA MultiSynth CLK1 R1 1 OSC VDDOB PLL XB MultiSynth R2 B CLK2 2 MultiSynth CLK3 R3 3 A0 VDDOC MultiSynth 2 R4 I C CLK4 4 SDA Interface MultiSynth CLK5 SCL R5 5 VDDOD MultiSynth R6 OEB CLK6 6 Control Logic MultiSynth CLK7 SSEN R7 7 20-QFN, 24-QSOP GN
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Si5351A/B/C VDD Si5351B VDDOA MultiSynth R0 XA 0 CLK0 PLL OSC MultiSynth CLK1 R1 XB 1 VDDOB MultiSynth VCXO R2 2 CLK2 VC MultiSynth CLK3 R3 3 VDDOC MultiSynth R4 SDA 2 CLK4 4 I C Interface MultiSynth CLK5 SCL R5 5 VDDOD MultiSynth R6 OEB Control CLK6 6 Logic SSEN CLK7 MultiSynth R7 7 20-QFN, 24-QSOP GND VDD Si5351C VDDOA MultiSynth R0 XA 0 CLK0 PLL OSC MultiSynth CLK1 A R1 XB 1 VDDOB MultiSynth R2 PLL CLK2 2 B CLKIN MultiSynth CLK3 R3 3 VDDOC MultiSynth R4 SDA 4 CLK4 2 I C CLK5 SCL Mul
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Si5351A/B/C 3. Functional Description 2 The Si5351 is a versatile I C programmable clock generator that is ideally suited for replacing crystals, crystal oscillators, VCXOs, PLLs, and buffers. A block diagram showing the general architecture of the Si5351 is shown in Figure 3. The device consists of an input stage, two synthesis stages, and an output stage. The input stage accepts an external crystal (XTAL), a clock input (CLKIN), or a control voltage input (VC) depending on the version of the
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Si5351A/B/C 3.1.2. External Clock Input (CLKIN) The external clock input is used as a clock reference for the PLLs when generating synchronous clock outputs. CLKIN can accept any frequency from 10 to 100 MHz. A divider at the input stage limits the PLL input frequency to 30 MHz. 3.1.3. Voltage Control Input (VC) The VCXO architecture of the Si5350B eliminates the need for an external pullable crystal. Only a standard, low- cost, fixed-frequency (25 or 27 MHz) AT-cut crystal is required. The tun
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Si5351A/B/C 3.4. Spread Spectrum Spread spectrum can be enabled on any of the clock outputs that use PLLA as its reference. Spread spectrum is useful for reducing electromagnetic interference (EMI). Enabling spread spectrum on an output clock modulates its frequency, which effectively reduces the overall amplitude of its radiated energy. See “AN554: Si5350/51 PCB Layout Guide” for details. Note that spread spectrum is not available on clocks synchronized to PLLB or to the VCXO. The Si5351 suppo
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Si5351A/B/C 2 4. I C Interface Many of the functions and features of the Si5351 are controlled by reading and writing to the RAM space using the 2 2 I C interface. The following is a list of the common features that are controllable through the I C interface. A summary of register functions is shown in Section 7. Read Status Indicators Loss of signal (LOS) for the CLKIN input Loss of lock (LOL) for PLLA and PLLB Configuration of multiplication and divider values for the PLLs, MultiSynt
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Si5351A/B/C Write Operation – Single Byte S Slv Addr [6:0] 0 A Reg Addr [7:0] A Data [7:0] A P Write Operation - Burst (Auto Address Increment) S Slv Addr [6:0] 0 A Reg Addr [7:0] A Data [7:0] A Data [7:0] A P Reg Addr +1 1 – Read From slave to master 0 – Write A – Acknowledge (SDA LOW) From master to slave N – Not Acknowledge (SDA HIGH) S – START condition P – STOP condition 2 Figure 9. I C Write Operation A read operation is performed in two stages. A data write is used to set the register ad
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Si5351A/B/C 5. Configuring the Si5351 2 The Si5351 is a highly flexible clock generator which is entirely configurable through its I C interface. The device’s default configuration is stored in non-volatile memory (NVM) as shown in Figure 11. The NVM is a one time programmable memory (OTP) which can store a custom user configuration at power-up. This is a useful feature for applications that need a clock present at power-up (e.g., for providing a clock to a processor). Power-Up NVM (OTP) RAM
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Si5351A/B/C Disable Outputs Set CLKx_DIS high; Reg. 3 = 0xFF Powerdown all output drivers Reg. 16, 17, 18, 19, 20, 21, 22, 23 = 0x80 Set interrupt masks (see register 2 description) Write new configuration to device using Register the contents of the register map Map generated by ClockBuilder Desktop. This step also powers up the output drivers. Use ClockBuilder (Registers 15-92 and 149-170) Desktop v3.1 or later Apply PLLA and PLLB soft reset Reg. 177 = 0xAC Enable desired outputs (see Reg
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Si5351A/B/C 5.2. Si5351 Application Examples The Si5351 is a versatile clock generator which serves a wide variety of applications. The following examples show how it can be used to replace crystals, crystal oscillators, VCXOs, and PLLs. 5.3. Replacing Crystals and Crystal Oscillators Using an inexpensive external crystal, the Si5351A can generate up to 8 different free-running clock frequencies for replacing crystals and crystal oscillators. A 3-output version packaged in a small 10-MSOP is
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Si5351A/B/C 5.4. Replacing Crystals, Crystal Oscillators, and VCXOs The Si5351B combines free-running clock generation and a VCXO in a single package for cost sensitive video applications. An example is shown in Figure 14. Free-running Clocks Ethernet XA CLK0 Multi 125 MHz PHY Synth 0 27 MHz OSC PLL CLK1 Multi 48 MHz XB USB Synth Controller 1 CLK2 Multi 28.322 MHz Synth HDMI 2 Port CLK3 Multi 74.25 MHz Synth VC 3 VCXO CLK4 Multi 74.25/1.001 MHz Video/Audio Synth Processor 4 CLK5 M
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Si5351A/B/C 5.6. Replacing a Crystal with a Clock The Si5351 can be driven with a clock signal through the XA input pin. V = 1 V IN PP Multi 25/27 MHz Synth XA PLLA 0 Multi 0.1 µF OSC Synth 1 XB PLLB Multi Synth Note: Float the XB input while driving N the XA input with a clock Figure 16. Si5351 Driven by a Clock Signal 5.7. HCSL Compatible Outputs The Si5351 can be configured to support HCSL compatible swing when the VDDO of the output pair of interest is set to 2.5 V (i.e., VDDOA mus
