Inhaltszusammenfassung zur Seite Nr. 1
C8051T620/2-DK
C8051T620/2 DEVELOPMENT KIT USER’S GUIDE
1. Kit Contents
The C8051T620 and C8051T622 Development Kits contain the following items:
C8051T62x Motherboard
C8051T62x Emulation Daughter Board with C8051F34A installed
Socket Daughter Board (one of the following):
C8051T62x QFN 32-pin (C8051T620DK)
C8051T622 QFN 24-pin (C8051T622DK)
Twenty device samples (one of the following):
C8051T620-GM (C8051T620DK)
C8051T622-GM (C8051T622DK)
C8051Txxx Development Kit Quick-Start
Inhaltszusammenfassung zur Seite Nr. 2
C8051T620/2-DK 3. Hardware Setup See Figure 1 for a diagram of the hardware configuration. 1. Attach the desired daughter board to the motherboard at connectors P1 and P2. 2. If using the QFN Socket Daughter Board, place the device to be programmed into the socket. 3. Place shorting blocks on J7 and the +3VD-VDD_PWR jumper pair on J6, as shown in Figure 1. 4. Connect the motherboard’s P5 USB connector to a PC running the Silicon Laboratories IDE using the USB Cable. 5. Connect the ac-to-dc pow
Inhaltszusammenfassung zur Seite Nr. 3
C8051T620/2-DK 4. Software Installation The included CD-ROM contains the Silicon Laboratories Integrated Development Environment (IDE), 8051 evaluation toolset, Virtual COM Port drivers for the CP210x USB to UART Bridge, and additional documentation. Insert the CD-ROM into your PC's CD-ROM drive. An installer will automatically launch, allowing you to install the IDE software or read documentation by clicking buttons on the installation panel. If the installer does not automatically start when
Inhaltszusammenfassung zur Seite Nr. 4
C8051T620/2-DK 5. Software Overview The following software is necessary to build a project, download code to, and communicate with the target microcontroller. 8051 Evaluation Toolset Silicon Labs Integrated Development Environment (IDE) Other useful software that is provided on the development kit CD and the Silicon Labs Downloads website ( www.silabs.com/mcudownloads) includes: Configuration Wizard 2 Keil µVision2, µVision3, and µVision4 Drivers MCU Production Programmer and Flash Pr
Inhaltszusammenfassung zur Seite Nr. 5
C8051T620/2-DK 6. Click the Connect button in the toolbar or select Debug Connect from the menu to connect to the device. 7. Download the project to the target by clicking the Download Code button in the toolbar. Note: To enable automatic downloading if the program build is successful, select Enable Automatic Con- nect/Download after Build in the Project Target Build Configuration dialog. If errors occur during the build process, the IDE will not attempt the download. 8. Click on the Go butt
Inhaltszusammenfassung zur Seite Nr. 6
C8051T620/2-DK The Configuration Wizard utility helps accelerate development by automatically generating initialization source code to configure and enable the on-chip resources needed by most design projects. In just a few steps, the wizard creates complete startup code for a specific Silicon Laboratories MCU. The program is configurable to provide the output in C or assembly language. For more information, refer to the Configuration Wizard 2 help available under the Help menu in Configuration
Inhaltszusammenfassung zur Seite Nr. 7
C8051T620/2-DK 6. Example Source Code Example source code and register definition files are provided by default in the SiLabs\MCU\Examples\C8051T620_1_T320_3 or SiLabs\MCU\Examples\C8051T622_3_T326_7 directory during IDE installation. These files may be used as a template for code development. 6.1. Register Definition Files Register definition files C8051T620.inc, C8051T622.inc, C8051T620_defs.h, C8051T622_defs.h, and compiler_defs.h define all SFR registers and bit-addressable control/status
Inhaltszusammenfassung zur Seite Nr. 8
C8051T620/2-DK 7. Development Boards The C8051T620/2 Development Kit includes a motherboard that interfaces to various daughter boards. The C8051T62x Emulation Daughter Board contains a C8051F34A device to be used for preliminary software development. The C8051T620 Socket Daughter Board and C8051T622 Socket Daughter Board allow programming and evaluation of the actual C8051T62x devices. Numerous input/output (I/O) connections are provided on the motherboard to facilitate prototyping. Figure 3 s
Inhaltszusammenfassung zur Seite Nr. 9
C8051T620/2-DK LED1 LED2 SW1 SW2 SILICON LABS J1 www.silabs.com P1.0 P0.1 P1.2 P0.6 SW1 LED1 SW2 LED2 P2.1 P2.0 P2.3 P2.2 J14 C8051T62x-MB P3 J9 J10 J2 J15 P1 VPP J7 J3 PWR J6 VDD_PWR +3VD VDD_PWR VDD_EXT VDD_PWR VDD_DEBUG J4 VDD_PWR VDD_COMM USB ACTIVE D10 D11 D12 P2 RUN STOP DEBUG J5 PWR U2 USB ACTIVE U1 CP2103 J8 F326 RTS_DEBUG CTS_DEBUG J12 J13 P1.1 P1.2 RTS_COMM CTS_COMM P5 J11 RX_DEBUG TX_DEBUG P0.4 P0.5 P4 RESET RX_COMM TX_COMM R8 Figure 3. C8051T62x Motherboard LED1 LED2 SW1 SW2 SILICON
Inhaltszusammenfassung zur Seite Nr. 10
C8051T620/2-DK C8051T62x EDB U1 P3 F34A SILICON LABS www.silabs.com VBUS VREGIN VDD VREGIN Figure 5. C8051T62x Emulation Daughter Board C8051T62x QFN32 SKT DB J3 SILICON LABS www.silabs.com J1 P3 J2 Figure 6. C8051T620 QFN32 Socket Daughter Board C8051T622 QFN24 SKT DB J3 SILICON LABS www.silabs.com J1 P3 J2 Figure 7. C8051T622 QFN24 Socket Daughter Board 10 Rev. 0.4 VDD VDD VDD VBUS VDD VBUS VIO VIO VREGIN VREGIN VREGIN VREGIN
Inhaltszusammenfassung zur Seite Nr. 11
C8051T620/2-DK C8051T320 QFP32 SKT DB SILICON LABS www.silabs.com J2 P3 J1 Figure 8. C8051T320 QFP32 Socket Daughter Board C8051T321 QFN28 SKT DB SILICON LABS www.silabs.com J2 P3 J1 Figure 9. C8051T321 QFN28 Socket Daughter Board C8051T326 QFN28 SKT DB J3 SILICON LABS www.silabs.com J1 P3 J2 Figure 10. C8051T326 QFN28 Socket Daughter Board Rev. 0.4 11 VDD VBUS VDD VBUS VDD VDD VBUS VREGIN VREGIN VREGIN VREGIN VIO VREGIN VREGIN
Inhaltszusammenfassung zur Seite Nr. 12
C8051T620/2-DK C8051T327 QFN28 SKT DB J3 SILICON LABS www.silabs.com J1 P3 Figure 11. C8051T327 QFN28 Socket Daughter Board 12 Rev. 0.4 VDD VBUS VREGIN VREGIN
Inhaltszusammenfassung zur Seite Nr. 13
C8051T620/2-DK 7.1. System Clock Sources The C8051T62x/32x devices feature a calibrated internal oscillator that is enabled as the system clock source on reset. After reset, the internal oscillator operates at a frequency of 48 MHz (±1.5%) by default but may be configured by software to operate at other frequencies. Therefore, in many applications, an external oscillator is not required. However, if you wish to operate the C8051T62x/32x device at a frequency not available with the internal osci
Inhaltszusammenfassung zur Seite Nr. 14
C8051T620/2-DK Table 2 lists the port pins and headers corresponding to the switches, LEDs, and potentiometer. Table 2. Motherboard I/O Descriptions Description Component Name I/O Header Switch SW1 Daughter Card's P0.1 J9 [2-4] Daughter Card’s P2.0 J9 [4-6] Switch SW2 Daughter Card’s P1.0 J9 [1-3] Daughter Card’s P2.1 J9 [3-5] RESET SW3 Daughter Card's RST/C2CK None Green LED labeled “LED1” D1 Daughter Card's P0.6 J10 [2-4] Daughter Card's P2.2 J10 [4-6] Green LED labeled “LED2” D2 Daughter Car
Inhaltszusammenfassung zur Seite Nr. 15
C8051T620/2-DK 7.4. USB Debug Adapter (DEBUG/P5) A Universal Serial Bus (USB) connector (P5) provides the onboard debug and programming interface. The debug/ programming MCU and associated circuitry are powered through the USB connector, which can also supply the rest of the motherboard by routing the USB Debug Adapter's power through J6. The USB Debug Adapter also provides a data communications interface that can be used when the debug adapter is not debugging or programming a C8051T62x/32x de
Inhaltszusammenfassung zur Seite Nr. 16
C8051T620/2-DK 7.8. Analog I/O (J1 and J14) Three of the C8051T62x/32x target device's port pins are connected to the J1 terminal block. The terminal block also allows users to input an external voltage that can be used as the power supply of the board. Refer to Table 3 for the J1 terminal block connections. Placing a shorting block on J14 will connect the P0.7/VREF signal on J1 to the P0.7 pin of the device. Table 3. J1 Terminal Block Descriptions Pin # Description 1VREGIN 2VIO 3GND 4 P2.5 (An
Inhaltszusammenfassung zur Seite Nr. 17
C8051T620/2-DK 7.10. Using Alternate Supplies with the C8051T62x Development Kit For most evaluation purposes, the onboard 3.3 V supply regulator is sufficient to be used as a VDD power supply. However, in applications where a different supply voltage is desired (e.g., 1.8 V), an external supply voltage can be applied to the board at the analog connector (J1). Some devices in the C8051T62x/32x family also support a separate voltage input for the input/output voltage of the port pins. This Volta
Inhaltszusammenfassung zur Seite Nr. 18
C8051T620/2-DK 8. Schematics 18 Rev. 0.4 Figure 14. C8051T62x Motherboard Schematic (1 of 2)
Inhaltszusammenfassung zur Seite Nr. 19
C8051T620/2-DK Rev. 0.4 19 Figure 15. C8051T62x Motherboard Schematic (2 of 2)
Inhaltszusammenfassung zur Seite Nr. 20
C8051T620/2-DK 20 Rev. 0.4 Figure 16. C8051T62x Emulation Daughter Board Schematic
