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ARM720T_LH79520 – Sharp LH79520 SoC
with ARM720T 32-bit RISC Processor
This document provides information on Altium Designer's Wishbone wrapper support
Summary
for the discrete Sharp Bluestreak® LH79520 – a fully integrated 32-bit System-on-
Chip (SoC), based on an ARM720T 32-bit RISC processor core.
Core Reference
CR0162 (v2.0) March 10, 2008
Altium Designer's ARM720T_LH79520 component is a 32-bit Wishbone-compatible RISC
The ARM720T macrocell within the
processor.
physical LH7
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ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor RISC Processor Background RISC, or Reduced Instruction Set Computer, is a term that is conventionally used to describe a type of microprocessor architecture that employs a small but highly-optimized set of instructions, rather than the large set of more specialized instructions often found in other types of architectures. This other type of processor is traditionally referred to as CISC, or Complex Instruction Set Comput
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ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor Improving and Extending Product Life-Cycles Fast time to market is usually synonymous with a weaker feature set – a traditional trade-off. With FPGA-based system designs you can have the best of both worlds. You can get your product to market quickly with a limited feature set, then follow-up with more extensive features over time, upgrading the product while it is already in the field. This not only extends product lif
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ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor Wishbone OpenBUS Processor Wrappers To normalize access to hardware and peripherals, each of the 32-bit processors supported in Altium Designer has a Wishbone OpenBUS-based FPGA core that 'wraps' around the processor. This enables peripherals defined in the FPGA to be used transparently with any type of processor. An FPGA OpenBUS wrapper around discrete, hard-wired peripherals also allows them to be moved seamlessly betw
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ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor Architectural Overview Symbol Figure 1. Symbols used for the ARM720T_LH79520 in both schematic (left) and OpenBus System (right). As can be seen from the schematic symbol in Figure 1, the ARM720T_LH79520 wrapper that is placed in an FPGA design essentially has three interfaces. The Wishbone External Memory and Peripheral I/O interfaces are identical to those of all other 32-bit processors supported by Altium Designer
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ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor Pin Description The following pin description is for the processor when used on the schematic. In an OpenBus System, although the same signals are present, the abstract nature of the system hides the pin-level Wishbone interfaces. The interface signals to the physical processor will be made available as sheet entries, associated with the parent sheet symbol used to reference the underlying OpenBus System. Table 1. ARM72
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ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor Name Type Polarity/Bus sizeDescription Peripheral I/O Interface Signals IO_STB_O Strobe signal. When asserted, indicates the start of a valid Wishbone O High data transfer cycle IO_CYC_O Cycle signal. When asserted, indicates the start of a valid Wishbone O High bus cycle. This signal remains asserted until the end of the bus cycle, where such a cycle can include multiple data transfers IO_ACK_I Standard Wishbone d
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ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor Name Type Polarity/Bus sizeDescription PER_RESET Reset signal from the LH79520. I Low ARM7_SYS_RESE Reset signal to the LH79520 (internally connected from the RST_I O Low T line). PER_CLK Clock signal from the LH79520 I Rise ARM7_SYS_CLK External Clock signal to the LH79520 (internally connected from the O Rise CLK_I line). PER_READY Static Memory Controller External Wait Control O Low PER_INT External Interrupt
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ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor Speed-critical (or latency-sensitive) parts of an application should also be placed in this memory space. The following memory sizes are available to choose from: • 1KB (256 x 32-bit Words) • 2KB (512 x 32-bit Words) • 4KB (1K x 32-bit Words) • 8KB (2K x 32-bit Words) • 16KB (4K x 32-bit Words) • 32KB (8K x 32-bit Words) • 64KB (16K x 32-bit Words) • 128KB (32K x 32-bit Words) • 256KB (64K x 32-bit Words) • 512KB
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ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor Memory & I/O Management The ARM720T_LH79520 uses 32-bit address buses providing a 4GByte linear address space. All memory access is in 32-bit words, which creates a physical address bus of 30-bits. Memory space is broken into seven main areas, as illustrated in Figure 4. Memory and peripheral I/O devices placed and wired within the FPGA design are mapped into the External Static Memory regions of this space. Further info
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ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor Figure 5. Memory devices mapped into banks 0- 4 (cs0-cs4) of the ARM720T_LH79520's addressable External Static Memory. Figure 6. Peripheral devices mapped into bank 5 (cs5) of the ARM720T_LH79520's addressable External Static Memory. CR0162 (v2.0) March 10, 2008 11
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ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor The adjacent flow chart shows the process that was followed to build this memory map in a schematic-based FPGA design. This flow chart is only a guide, during the course of development it Place Processor is likely that you will jump back and forth through this process as you build up the design. Dedicated System Interconnect Components This process of being able to quickly build up the design and resolve the processor to
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ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor • cs0 (Bank 0) – 4000_0000h to 43FF_FFFFh • cs1 (Bank 1) – 4400_0000h to 47FF_FFFFh The bank select signals • cs2 (Bank 2) – 4800_0000h to 4BFF_FFFFh arrive at the processor's wrapper component in • cs3 (Bank 3) – 4C00_0000h to 4FFF_FFFFh the FPGA on the • cs4 (Bank 4) – 5000_0000h to 53FF_FFFFh PER_CS bus. • cs5 (Bank 5) – 5400_0000h to 57FF_FFFFh • cs6 (Bank 6) – 5800_0000h to 5BFF_FFFFh The block of addresses
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ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor The size of the RAM can vary between 1KB and 16MB, dependent on the availability of embedded block RAM in the target FPGA device used. Memory size is configured in the Internal Processor Memory region of the Configure (32-bit Processors) dialog (see the section Configuring the Processor). Covering the processor's address space between 0000_0000h and 00FF_FFFFh, it will contain the reset and interrupt vectors, as well as
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ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor clock signal (CLK_I), an acknowledge signal fails to appear from the addressed slave peripheral device, the wait request to the ARM720T is dropped, the processor times out normally and the current data transfer cycle is forcibly terminated. The ACK_O signal from a slave peripheral should not be used as a ‘long delay’ hand-shaking mechanism. Where such a mechanism needs to be implemented, either use polling or interrupts.
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ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor • for an unsigned read, the processor will pad-out the remaining 24 or 16 bits respectively with zeroes • for a byte load/store, the processor will sign-extend from bit 8 • for a half-word load/store, the processor will sign-extend from bit 16. Peripheral I/O For memory I/O the process described happens transparently, because memory devices are always seen by the processor as 32 bits wide. Even when connecting to small
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ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor Hardware Description For detailed information about the hardware and functionality of the ARM720T_LH79520 processor, including internal registers, refer to the following reference guide, available from the ARM website: • ARM720T Technical Reference Manual Clocking The signal ARM7_SYS_CLK sent from the processor wrapper to the physical processor itself is simply the internally-routed CLK_I signal. On the physical devic
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ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor Wishbone Communications The following sections detail the standard handshaking that takes place when the processor communicates to a slave peripheral or memory device connected to the relevant Wishbone interface port. Both of the ARM720T_LH79520's Wishbone ports can be configured for 8-, 16- or 32-bit data transfer, depending on the width of the data bus supported by the connected slave device. Configuration is achieved
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ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor Reading from a Slave Wishbone Memory Device Data is read by the host processor (Wishbone Master) from a Wishbone-compliant memory device or memory controller (Wishbone Slave) in accordance with the standard Wishbone data transfer handshaking protocol. This data transfer cycle can be summarized as follows: • The host presents an address on its ME_ADR_O output for the address in memory that it wishes to read. It then nega
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ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor Placing an ARM720T_LH79520 in an FPGA design How the ARM720T_LH79520 is placed and wired within an FPGA design depends on the method used to build that design. The main processor-based system can be defined purely on the schematic sheet, or it can be contained as a separate OpenBus System, which is then referenced from the top-level schematic. The following sections take a look at using the processor in both of these des
