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DS5001FP
128k Soft Microprocessor Chip
www.maxim-ic.com
FEATURES PIN ASSIGNMENT (Top View)
8051-compatible microprocessor adapts to its
task
– Accesses up to 128kB of nonvolatile
SRAM
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
– In-system programming through on-chip
P0.4AD4 1 64 P2.6/A14
CE2 2 63 CE3
serial port
PE2 3 62 CE4
BA9 4 61 BD3
– Can modify its own program or data
P0.3/AD3 5 60 P2.5/A13
memory BA8 6 59 BD2
P0.2/AD2 7 58 P2.4/A12
– Accesses memory on a separate byte-wide
BA13 8 5
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DS5001FP DESCRIPTION The DS5001FP 128k soft microprocessor chip is an 8051-compatible microprocessor based on NV RAM technology and designed for systems that need large quantities of nonvolatile memory. It provides full compatibility with the 8051 instruction set, timers, serial port, and parallel I/O ports. By using NV RAM instead of ROM, the user can program and then reprogram the microprocessor while in-system. The application software can even change its own operation, which allows frequent
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DS5001FP Figure 1. BLOCK DIAGRAM 3 of 26
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DS5001FP PIN DESCRIPTION 80-PIN 44-PIN SIGNAL DESCRIPTION MQFP MQFP 11, 9, 7, General-Purpose I/O Port 0. This port is open-drain and cannot drive a logic 1. It requires 31 5, 1, 79, P0.0–P0.7 external pullups. Port 0 is also the multiplexed expanded address/data bus. When used in (P0.5) 77, 75 this mode, it does not require pullups. 15, 17, 19, 21, 44 P1.0–P1.7 General-Purpose I/O Port 1 25, 27, (P1.3) 29, 31 49, 50, 51, 56, General-Purpose I/O Port 2. Also serves as the MSB of the address in e
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DS5001FP 33, 35, 9 and A15 respectively. 37 Byte-Wide Data-Bus Bits 7–0. This 8-bit, bidirectional bus is combined with the 71, 69, 28, 26, nonmultiplexed address bus (BA14–0) to access NV SRAM. Decoding is performed on 67, 65, 24, 23, BD7–0 61, 59, 21, 20, CE1 and CE2 . Read/write access is controlled by R/ W . BD7–0 connect directly to an 57, 55 19, 18 SRAM, and optionally to a real-time clock or other peripheral. Read/Write. This signal provides the write enable to the SRAMs on the byte-wide
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DS5001FP INSTRUCTION SET The DS5001FP executes an instruction set that is object code-compatible with the industry standard 8051 microcontroller. As a result, software development packages such as assemblers and compilers that have been written for the 8051 are compatible with the DS5001FP. A complete description of the instruction set and operation are provided in the Secure Microcontroller User’s Guide. Also note that the DS5001FP is embodied in the DS2251T module. The DS2251T combines the DS5
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DS5001FP Figure 3. MEMORY MAP IN PARTITIONABLE MODE (PM = 0) Note: Partitionable mode is not supported when MSEL pin = 0 (128kB mode). 7 of 26
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DS5001FP Figure 4. MEMORY MAP WITH PES = 1 8 of 26
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DS5001FP Figure 5 illustrates a typical memory connection for a system using a 128kB SRAM. Note that in this configuration, both program and data are stored in a common RAM chip Figure 6 shows a similar system with using two 32kB SRAMs. The byte-wide address bus connects to the SRAM address lines. The bidirectional byte-wide data bus connects the data I/O lines of the SRAM. Figure 5. CONNECTION TO 128k x 8 SRAM 9 of 26
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DS5001FP Figure 6. DS5001FP CONNECTION TO 64k x 8 SRAM POWER MANAGEMENT The DS5001FP monitors V to provide power-fail reset, early warning power-fail interrupt, and switch CC over to lithium backup. It uses an internal bandgap reference in determining the switch points. These are called V , V , and V , respectively. When V drops below V , the DS5001FP performs an PFW CCMIN LI CC PFW interrupt vector to location 2Bh if the power-fail warning was enabled. Full processor operation continues regardl
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DS5001FP ABSOLUTE MAXIMUM RATINGS* Voltage Range on Any Pin Relative to Ground -0.3V to (V + 0.5V) CC Voltage Range on V Related to Ground -0.3C to 6.0C CC Operating Temperature Range -40C to +85C 1 Storage Temperature Range -55C to +125C Soldering Temperature See IPC/JEDEC J-STD-020A * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolu
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DS5001FP DC CHARACTERISTICS (continued) (T = 0°C to +70°C; V = 5V ±10%) A CC PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Input Leakage Current I +10 µA IL 0.45 < V < V (Port 0, MSEL) IN CC RST Pulldown Resistor R 40 150 k RE (0°C to +70°C) RST Pulldown Resistor R 30 180 10 k RE (-40°C to +85°C) R 4.7 k VRST Pullup Resistor VR R 40 PROG Pullup Resistor k PR Power-Fail Warning Voltage V 4.25 4.37 4.50 V 1 PFW (0°C to +70°C) Power-Fail Warning Voltage V 4.1 4.37 4.6 V 1, 10 PFW (-40°C
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DS5001FP AC CHARACTERISTICS EXPANDED BUS MODE TIMING SPECIFICATIONS (T = 0°C to +70°C; V = 5V ±10%) A CC # PARAMETER SYMBOL MIN MAX UNITS 1 Oscillator Frequency 1/ t 1.0 16 MHz CLK 2 ALE Pulse Width t 2t - 40 ns ALPW CLK 3 Address Valid to ALE Low t t - 40 ns AVALL CLK 4 Address Hold After ALE Low t t - 35 ns AVAAV CLK ALE Low to Valid Instruction In ns 5 at 12MHz t 4t -
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DS5001FP EXPANDED PROGRAM-MEMORY READ CYCLE EXPANDED DATA-MEMORY READ CYCLE 14 of 26
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DS5001FP EXPANDED DATA-MEMORY WRITE CYCLE 15 of 26
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DS5001FP AC CHARACTERISTICS (continued) EXTERNAL CLOCK DRIVE (T = 0°C to +70°C; V = 5V ±10%) A CC # PARAMETER SYMBOL MIN MAX UNITS External Clock-High Time 28 at 12MHz t 20 ns CLKHPW at 16MHz 15 External Clock-Low Time 29 at 12MHz t 20 ns CLKLPW at 16MHz 15 External Clock-Rise Time 30 at 12MHz t 20 ns CLKR at 16MHz 15 External Clock-Fall Time 31 at 12MHz t 20 ns CLKF at 16MHz 15 EXTERNAL CLOCK TIMING 16 of 26
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DS5001FP AC CHARACTERISTICS (continued) POWER CYCLE TIME (T = 0°C to +70°C; V = 5V ±10%) A CC # PARAMETER SYMBOL MIN MAX UNITS 32 Slew Rate from V to V t 130 µs CCMIN LI F 33 Crystal Startup Time t (Note 9) CSU 34 Power-On Reset Delay t 21,504 t POR CLK POWER CYCLE TIMING 17 of 26
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DS5001FP AC CHARACTERISTICS (continued) SERIAL PORT TIMING, MODE 0 (T = 0°C to +70°C; V = 5V ±10%) A CC # PARAMETER SYMBOL MIN MAX UNITS 35 Serial-Port Clock-Cycle Time t 12t µs CLK SPCLK 36 Output-Data Setup to Rising-Clock Edge t 10t - 133 ns DOCH CLK 37 Output-Data Hold After Rising-Clock Edge t 2t - 117 ns CHDO CLK 38 Clock-Rising Edge to Input-Data Valid t 10t - 133 ns CHDV CLK 39 Input-Data Hold After Rising-Clock Edge t 0ns CHDIV SERIAL PORT TIMING, MODE 0 18 of 26
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DS5001FP AC CHARACTERISTICS (continued) BYTE-WIDE ADDRESS/DATA BUS TIMING (T = 0°C to +70°C; V = 5V ±10%) A CC # PARAMETER SYMBOL MIN MAX UNITS Delay to Byte-Wide Address Valid from 40 t 30 ns CE1 , CE2 , or CE1N Low During Op Code CE1LPA Fetch 41 t 4t - 35 ns Pulse Width of CE 1-4, PE 1-4 or CE1N CEPW CLK Byte-Wide Address Hold After CE1 , CE2 , or 42 t 2t - 20 ns CE1HPA CLK CE1N High During Op Code Fetch Byte-Wide Data Se
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DS5001FP BYTE-WIDE BUS TIMING RPC AC CHARACTERISTICS, DBB READ (T = 0°C to +70°C; V = 5V ±10%) A CC # PARAMETER SYMBOL MIN MAX UNITS 54 t 0ns AR CS , A Setup to RD 0 55 t 0ns CS , A Hold After RD RA 0 56 t 160 ns RD Pulse Width RR 57 t 130 ns AD CS , A to Data-Out Delay 0 58 t 0 130 ns RD to Data-Out Delay RD 59 t 85 ns RD to Data-Float Delay RDZ 20 of 26
