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®
Intel IXF1104 4-Port Gigabit Ethernet
Media Access Controller
Datasheet
®
The Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller (hereafter referred to as
the IXF1104 MAC) supports IEEE 802.3* 10/100/1000 Mbps applications. The IXF1104 MAC
supports a System Packet Interface Phase 3 (SPI3) system interface to a network processor or
ASIC, and concurrently supports copper and fiber physical layer devices (PHYs).
The copper PHY interface supports the standard and reduced pin-count G
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® INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE,
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Contents Contents 1.0 Introduction..................................................................................................................................20 1.1 What You Will Find in This Document ................................................................................20 1.2 Related Documents ............................................................................................................20 2.0 General Description .....................................................
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Contents 5.1.5.1 Speed.....................................................................................................78 5.1.5.2 Duplex....................................................................................................78 5.1.5.3 Copper Auto-Negotiation .......................................................................78 5.1.6 Jumbo Packet Support ..........................................................................................78 5.1.6.1 Rx Statistics .........
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Contents 5.6.2.3 Receiver Operational Overview ...........................................................105 5.6.2.4 Selective Power-Down.........................................................................105 5.6.2.5 Receiver Jitter Tolerance .....................................................................105 5.6.2.6 Transmit Jitter ......................................................................................106 5.6.2.7 Receive Jitter .........................................
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Contents 6.0 Applications...............................................................................................................................130 6.1 Change Port Mode Initialization Sequence.......................................................................130 6.2 Disable and Enable Port Sequences................................................................................131 6.2.1 Disable Port Sequence.............................................................................
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Contents 9.0 Mechanical Specifications........................................................................................................224 9.1 Overview...........................................................................................................................224 9.1.1 Features...............................................................................................................224 9.2 Package Specifics ................................................................
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Contents 37 RGMII Interface Timing ............................................................................................................ 141 38 1000BASE-T Transmit Interface Timing...................................................................................142 39 1000BASE-T Receive Interface Timing.................................................................................... 143 40 SerDes Timing Diagram ..........................................................................
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Contents 25 RMON Additional Statistics.........................................................................................................81 26 GMII Interface Signal Definitions ................................................................................................95 27 RGMII Signal Definitions.............................................................................................................97 28 TX_ER and RX_ER Coding Description..........................................
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Contents 75 FC TX Timer Value ($ Port_Index + 0x07) ...............................................................................164 76 FD FC Address ($ Port_Index + 0x08 – + 0x09) ......................................................................164 77 IPG Receive Time 1 ($ Port_Index + 0x0A) ............................................................................. 165 78 IPG Receive Time 2 ($ Port_Index + 0x0B) .........................................................................
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Contents 125 RX FIFO Errored Frame Drop Counter Ports 0 - 3 ($0x5A2 - 0x5A5) ......................................198 126 RX FIFO SPI3 Loopback Enable for Ports 0 - 3 ($0x5B2)........................................................199 127 RX FIFO Padding and CRC Strip Enable ($0x5B3) .................................................................200 128 RX FIFO Transfer Threshold Port 0 ($0x5B8) ..........................................................................201 129 RX FIFO Transfer
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Contents Revision History Revision Number: 009 Revision Date: 27-Oct-2005 Page # Description 71 Modified Figure 8 “Ethernet Frame Format” [changed Preamble byte count to 7 bytes]. 136 Section 45, “RGMII Power” [changed V to V I and I ] CC DD in IH IL Added bullet to Section 5.7.3, “I²C Module Configuration Interface”: The I2C interface only 110 supports random single-byte reads and does not guarantee coherency when reading two-byte registers. 227 Replaced Figure 57 “FC-PBGA Package (Top and B
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Contents Revision Number: 008 Revision Date: August 1, 2005 (Sheet 2 of 2) Page # Description Modified Table 89 “TX Config Word ($ Port_Index + 0x17)” [changed default value for the 170 register from “0x0001A0” to “0x000001A0” and changed default value for bit 6 (Half Duplex) from 1 to 0]. Modified Table 95 “PHY Control ($ Port Index + 0x60)” [added “Need one-sentence 181 descriptions of register” and register default value]. Modified Table 96 “PHY Status ($ Port Index + 0x61)” [added “Need o
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Contents Revision Number: 007 Revision Date: March 24, 2004 (Sheet 1 of 5) Page # Description All Globally replaced GBIC with Optical Module Interface. All Globally edited signal names. Globally changed SerDes and PLL analog power ball names as follows: TXAVTT and RXAVTT changed to AVDD1P8_2 TXAV25 and RXAV25 changed to AVDD2P5_2 All PLL1_VDDA and PLL2_VDDA changed to AVDD1P8_1 PLL3_VDDA changed to AVDD2P5_1 PLL1_GNDA, PLL2_GNDA, and PLL3_GNDA changed to GND Reworded and rearranged the Product
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Contents Revision Number: 007 Revision Date: March 24, 2004 (Sheet 2 of 5) Page # Description Modified Section 4.3, “Signal Description Tables” [changed heading from “Signal Naming 39 Conventions; added new headings Section 4.1.1, “Signal Name Conventions” and Section 4.1.2, “Register Address Conventions”; and added/enhanced material under headings. Added new Section 4.5, “Multiplexed Ball Connections” with Table 16 “Line Side Interface 58 Multiplexed Balls” and Table 17 “SPI3 MPHY/SPHY Inte
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Contents Revision Number: 007 Revision Date: March 24, 2004 (Sheet 3 of 5) Page # Description 98 Modified Figure 19 “TX_CTL Behavior” [changed signal names]. 98 Modified Figure 20 “RX_CTL Behavior” [changed signal names]. Modified Section 5.5, “MDIO Control and Interface” [changed 3.3 us to 3.3 ms in fourth paragraph, 99 third sentence]. Modified/replaced all text under Section 5.6, “SerDes Interface” on page 103 [added Table 29 103 “SerDes Driver TX Power Levels”]. NA Removed old Section 5.6
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Contents Revision Number: 007 Revision Date: March 24, 2004 (Sheet 4 of 5) Page # Description Broke up the old Register Map into Table 59 “MAC Control Registers ($ Port Index + Offset)”, Table 60 “MAC RX Statistics Registers ($ Port Index + Offset)”, Table 61 “MAC TX Statistics Registers ($ Port Index + Offset)”, Table 62 “PHY Autoscan Registers ($ Port Index + Offset)”, 156 Table 63 “Global Status and Configuration Registers ($ 0x500 - 0X50C)”, Table 64 “RX FIFO Registers ($ 0x580 - 0x5BF)
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Contents Revision Number: 007 Revision Date: March 24, 2004 (Sheet 5 of 5) Page # Description Modified Table 136 “Loop RX Data to TX FIFO (Line-Side Loopback) Ports 0 - 3 ($0x61F)” 207 [renamed heading and bit name]. Modified Table 138 “TX FIFO Overflow Frame Drop Counter Ports 0 - 3 ($0x621 – 0x624)” 208 [renamed from TX FIFO Number of Frames Removed Ports 3 - 0]. Modified Table 139 “TX FIFO Errored Frame Drop Counter Ports 0 - 3 ($0x625 – 0x629)” [renamed 209 from TX FIFO Number of Dropped
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Contents Revision Number: 006 Revision Date: August 21, 2003 (Sheet 2 of 2) Page # Description Modified Table 53 “IPG Receive and Transmit Time Register (Addr: Port_Index + 0x0A – + 140 0x0C)”. 143 Modified Table 60 “Short Runts Threshold Register (Addr: Port_Index + 0x14)”. 143 Modified Table 61 “Discard Unknown Control Frame Register (Addr: Port_Index + 0x15)”. 143 Modified Table 62 “RX Config Word Register Bit Definition (Addr: Port_Index + 0x16)”. 145 Modified Table 64 “DiverseConfigWrite
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® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller 1.0 Introduction This document contains information on the IXF1104 MAC, a four-port Gigabit Media Access Controller that supports IEEE 802.3 10/100/1000 Mbps applications. 1.1 What You Will Find in This Document This document contains the following sections: � Section 2.0, “General Description” on page 21 provides the block diagram system architecture. � Section 3.0, “Ball Assignments and Ball List Tables” on page 23 shows the sig
