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Intel® 460GX Chipset System
Software Developer’s Manual
June 2001
Document Number: 248704-001
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THIS DOCUMENT IS PROVIDED “AS IS” WITH NO WARRANTIES WHATSOEVER, INCLUDING ANY WARRANTY OF MERCHANTABILITY, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY WARRANTY OTHERWISE ARISING OUT OF ANY PROPOSAL, SPECIFICATION OR SAMPLE. Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such produ
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Contents 1 Introduction......................................................................................................................1-1 1.1 System Overview ...............................................................................................1-1 1.1.1 Component Overview............................................................................1-2 1.2 Product Features................................................................................................1-3 1.3 Itanium™
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3 System Architecture ........................................................................................................3-1 3.1 Coherency..........................................................................................................3-1 3.1.1 Processor Coherency............................................................................3-1 3.1.2 PCI Coherency......................................................................................3-2 3.1.3 AGP Coherency .............
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6.1.6 Private Bus between SAC and SDC .....................................................6-2 6.2 Memory ECC Routing ........................................................................................6-3 6.3 Data Poisoning...................................................................................................6-3 6.4 Usage of First-error and Next-error ....................................................................6-3 6.4.1 Masked Bits........................................
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7.2 AGP Traffic.........................................................................................................7-6 7.2.1 Addresses Used by the Graphics Card.................................................7-6 7.2.2 Traffic Priority ........................................................................................7-7 7.2.3 Coherency, Translation and Types of AGP Traffic................................7-7 7.2.4 Ordering Rules .........................................................
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8.2.14 Extended Hot-Plug Miscellaneous ......................................................8-18 9 IFB Register Mapping......................................................................................................9-1 9.1 PCI / LPC / FWH Configuration..........................................................................9-1 9.1.1 PCI Configuration Registers (Function 0)..............................................9-1 9.2 IDE Configuration..............................................
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11.1.16 Deterministic Latency Control Register (Function 0)...........................11-7 11.1.17 MGPIOC–Muxed GPIO Control (Function 0) ......................................11-8 11.1.18 PDMACFG–PCI DMA Configuration Resister (Function O)................11-8 11.1.19 DDMABP–Distributed DMA Slave Base Pointer Registers (Function 0).........................................................................11-8 11.1.20 RTCCFG–Real Time Clock Configuration Register (Function 0)........11-9 11.1.21 GP
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13.2.4 PCISTS–PCI Device Status Register (Function 2)..............................13-3 13.2.5 RID–Revision Identification Register (Function 2)...............................13-3 13.2.6 CLASSC–Class Code Register (Function 2).......................................13-4 13.2.7 MLT–Master Latency Timer Register (Function 2)..............................13-4 13.2.8 HEDT–Header Type Register (Function 2) .........................................13-4 13.2.9 USBBA–USB I/O Space Base Address (Function
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15 PCI/LPC Bridge Description..........................................................................................15-1 15.1 PCI Interface ....................................................................................................15-1 15.1.1 Transaction Termination .....................................................................15-1 15.1.2 Parity Support .....................................................................................15-1 15.1.3 PCI Arbitration.............
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7-4 GART Entry Format for 4 MB Pages..................................................................7-3 7-5 GART SRAM Timings ........................................................................................7-5 Tables 1-1 Intel® 460GX Chipset Components ...................................................................1-2 2-1 Device Mapping on Bus CBN.............................................................................2-2 2-2 Memory-Mapped Register Summary .....................
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10-10 Ultra DMA Timing Value Based on Drive Mode .............................................10-11 10-11 Ultra DMA/Multi Word DMA/Single Word Transfer/Mode Values ..................10-12 10-12 PIO Transfer/Mode Values.............................................................................10-12 10-13 Drive Capabilities Checklist............................................................................10-13 10-14 IFB Settings Checklist ......................................................
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Introduction 1 This document provides information about the Intel® 460GX chipset components. The 460GX chipset is a high performance memory and I/O chipset for the Intel Itanium™ processor, targeted for multiprocessor server and high-end workstation designs. This document describes the software programmer's interface to the 460GX chipset. It provides a brief summary of the system architecture supported by the 460GX chipset, a list of features within the chipset and a detailed description of
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Introduction 1.1.1 Component Overview Table 1-1 lists the 460GX chipset components. Table 1-1. Intel® 460GX Chipset Components Component Name Function SAC 82461GX Interfaces the address and control portion of the Itanium™ processor system bus and the memory bus. Acts as a host bridge interface to System Address peripheral I/O devices through four Expander busses. Controller SDC 82462GX Interfaces the data portion of the Itanium processor system bus and the memory bus. System Data path Cont
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Introduction 1.2 Product Features High performance hardware based on IA-64 High bandwidth system bus for multiprocessor architecture scalability — 4.2 GB/s memory bandwidth can — Support of the Intel® Itanium™ processor simultaneously support both the full system 64-bit data bus bus and the full I/O bus bandwidths — Full support for 4-way multiprocessing — Architectural support for 64 MB to 64 GB of — 266 MHz data bus frequency SDRAM — Cache line size of 64 bytes — Support for up to four
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Introduction 1.4 DRAM Interface Support SDRAM 3.3 volt, 168-pin DIMM’s are the only memory type supported. Support for 64 MB to 64 GB of DRAM. Minimum memory size is 64 MB using 16 MB DIMM’s. Minimum incremental size is 64 MB using 16 MB DIMM’s. Maximum memory size is 16 GB using 128 MB DIMM’s. Maximum memory size is 64 GB using 1 GB DIMM’s. Only 3.3 volt memory is supported. Support for Auto Detection of SDRAM Memory Type. Supports 16, 64, 128 and 256 Mbit DRAM devices. Mi
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Introduction Parity protection on all PCI signals. Data collection & write assembly. — Combines back-to-back sequential processor-to-PCI memory writes to PCI burst writes. — Processor to PCI write assembly of full/partial line writes. Two outbound read requests containing a total of two cache lines of read data for each PCI bus. Supports six outbound write requests containing a total of three cache lines of write data for each 32 bit PCI bus. Supports 12 outbound write requests contai
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Introduction I2C Slave Interface will allow viewing and modifying of specific error and configuration registers. 1.7 Other Platform Components These 460GX devices provide access to flash space, interrupt collection and legacy features. 1.7.1 I/O & Firmware Bridge (IFB) The 460GX chipset is designed to work with the IFB south bridge. As part of this support, the PXB includes an internal PCI arbiter as well as support for an external PCI arbiter. The IFB consists of an 8259C Interrupt contr
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Introduction JTAG IEEE 1149.1 Specification (http://www.ieee.com) Universal Serial Bus Specification (http://www.usb.org) System Management Bus Specification, Rev. 1.0 Low Pin Count (LPC) Interface Specification, Rev 1.0 Note: Contact your Intel representative for the latest revision of the documents without document numbers. 1.9 Revision History Date Description June 2001 Initial release. Intel® 460GX Chipset Software Developer’s Manual 1-7
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Introduction 1-8 Intel® 460GX Chipset Software Developer’s Manual
