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®
Intel 80303 and 80302 I/O
Processors
Specification Update
May 6, 2003
® ®
Notice: The Intel 80303 and Intel 80302 I/O Processors processor may contain design defects
or errors known as errata. Characterized errata that may cause the product’s behavior to deviate
from pubished specifications are documented in this specification update.
Order Number: 273355-010
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INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE,
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Contents Revision History ......................................................................................... 5 Preface....................................................................................................... 7 Summary Table of Changes....................................................................... 8 Identification Information.......................................................................... 14 Errata ............................................................
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This Page Intentionally Left Blank ® 4 Intel 80303 and 80302 I/O Processors Specification Update
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Revision History Revision History sc Date Version Description Added Errata 2. 05/01/03 010 Revised Specification Clarifications 4, 7 and 8. Reworded Specification Clarification 4. 08/27/02 009 Added Specification Clarifications 7 and 8. Added Specification Clarifications 5 and 6. 11/15/01 008 Added Document Changes 32 and 33. Added Specification Clarification 4. 08/22/01 007 Added Document Changes 30 and 31. Added Document Changes 25 through 29. 04/24/01 006 Revised Device ID Registers “A-2” Rev
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Preface Preface This document is an update to the specifications contained in the Affected Documents/Related Documents table below. This document is a compilation of device and documentation errata, specification clarifications and changes. It is intended for hardware system manufacturers and software developers of applications, operating systems, or tools. Information types defined in Nomenclature are consolidated into the specification update and are no longer published in other documents.
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Summary Table of Changes Summary Table of Changes The following table indicates the errata, specification changes, specification clarifications, or ® ® documentation changes which apply to the Intel 80303 and Intel 80302 I/O Processors product. Intel may fix some of the errata in a future stepping of the component, and account for the other outstanding issues through documentation or specification changes as noted. This table uses the following notations: Codes Used in Summary Table Stepping
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Summary Table of Changes Errata Steppings No. Page Status Errata A-0 A-1 A-2 Single-bit and Multi-bit Error Reporting Cannot Be 1 XXX 12 NoFix Individually Enabled by ECC Control Register Instruction Sequence Can Scoreboard a Register 2 XXX 12 NoFix Indefinitely Specification Changes Steppings No. Page Status Specification Changes A-2 #-# #-# 1 X 14 Doc Summary of the Intel® 80302 I/O Processor Specification Clarifications Steppings No. Page Status Specification Clarifications A-0 A-1 A-2 1 XX
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Summary Table of Changes Documentation Changes No. Document Revision Page Status Documentation Changes 1 272353-001 17 Doc Title Page revision number 2 272353-001 17 Doc Figure 9-3 on pg 9-9 did not print correctly 3 272353-001 18 Doc Figure 13-22 on pg 13-40 did not print correctly 4 272353-001 18 Doc Figure 13-18, pg 13-35 5 272353-001 19 Doc Figure 15-2 on pg 15-3 did not print correctly 6 272353-001 20 Doc Incorrect Vendor ID in ATU register 7 272353-001 20 Doc Section 23.2 on pg 23-2 has in
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Identification Information Identification Information Markings Topside Markings GC80303 SSSSSS MALAY FFFFFFFF-[{SN}] M © ‘2000 INTEL ® Intel 80303 I/O Processor Die Details ® Intel ® QDF/ i960 Core Voltage Part Number Stepping Spec Processor Notes (V) Number Speed (MHz) GC80303 A-0 Q176 3.3 100 Samples - limited testing GC80303 A-0 Q196 3.3 100 Samples - limited testing GC80303 A-1 Q189 3.3 100 Samples - limited testing GC80303 A-1 SL4Q4 3.3 100 Production Production - Yield GC80303 A-2 SL57
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Identification Information Device ID Registers Address Processor PCI-to-PCI ® ® Translation Unit Intel i960 Core Processor Device and Device ID Bridge Unit Revision ID Device ID Stepping Register Revision ID Register (DEVICEID - 0xFF00 8710) (PDIDR - 0x1710) (RIDR - 0x1008) (ATURID - 0x1208) 80303 A-0 08879013 0x00 0x00 00823013 80303 A-1 18879013 0x01 0x01 00823013 80303 A-2 18879013 0x01 0x01 00823013 80302 A-2 18878013 0x01 0x01 00823013 NOTE: There are no functionality differences betwe
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Errata Errata 1. Single-bit and Multi-bit Error Reporting Cannot Be Individually Enabled by ECC Control Register Problem: The ECC Control Register ECCR is described as having the ability to select multi-bit error and/or ® single-bit error reporting (see Table 13-24 on page 13-31 of the Intel 80303 I/O Processor Developer’s Manual). However, the algorithm does not allow individual enabling; that is, the reporting is either on or off for both multi-bit and single bit error reporting. Implicati
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Errata Nominally, the emul multiplies two 32-bit operands to produce a long ordinal (64-bit) result stored in two adjacent registers. When the errata occurs, the low-order register receives the correct value, but the high-order register becomes scoreboarded indefinitely. The scoreboarded register is always odd-numbered (i.e., g1, g3, g5, ..., r7, r9, r11, ...) since the emul instruction always directs the high-order result to the odd-numbered register of the destination pair. In some cases,
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Specification Changes Specification Changes 1. Summary of the Intel® 80302 I/O Processor Problem: The Intel® 80302 I/O processor is based on the A-2 stepping of the Intel® 80303 I/O processor. The 80302 I/O processor is identical to the 80303 I/O processor, except the SDRAM and internal 2 2 bus run at 66 MHz. For applications that use the I C unit, the I C clock is generated from the 2 internal bus clock, so the ICCR (I C Clock Count Register) needs to be properly adjusted. The Device ID Regi
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Specification Clarifications Specification Clarifications 1. ECC is Always Enabled Problem: ECC is always enabled, therefore do not design an Intel® 80303 I/O processor based product without ECC implemented, this causes severe system errors. On the Intel® 80960RM/RN I/O processors, ECCR.3 can be cleared to disable ECC, but with the 80303 I/O processor, ECCR.3 is reserved. 2. 32-bit SDRAM is Not Supported Problem: The memory controller on the 80303 I/O processor supports between 32 and 512 Mby
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Specification Clarifications 6. SREQ64# Functionality Problem: There is an SREQ64# functionality difference between the A-1 and A-2 steppings of the 80303 I/O processors. (This functionality is also on the 80302 since it is based on the A-2 stepping.) During the power up sequence, the S_REQ64# signal is sampled by PCI devices on the secondary PCI bus to determine 64-bit or 32-bit PCI operation. On the A-1 stepping, S_REQ64# is deasserted one P_CLK after the deassertion of S_RST# (as stated i
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Documentation Changes Documentation Changes 1. Title Page revision number Issue: Manual indicates Revision 0.5. Implication: This type of revision numbering is not used with published documents. Refer to the Document Number 272353-001. The extension -001 is the correct revision number for this document. Workaround: Ignore revision number 0.5. ® Affected Docs: Intel 80303 I/O Processor Developer’s Manual. 2. Figure 9-3 on pg 9-9 did not print correctly Problem: Figure 9-3 on pg 9-9 did not print
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Documentation Changes 3. Figure 13-22 on pg 13-40 did not print correctly Problem: Figure 13-22 on pg 13-40 did not print correctly. Workaround: Replace Figure 13-22 with the following: out SCKE PULLCKE = 1 PULLCKE = 0 P_RST# A6814-01 ® Affected Docs: Intel 80303 I/O Processor Developer’s Manual. 4. Figure 13-18, pg 13-35 Problem: Replace Figure 13-18 with the following: I_CLK SDQ(71:0) SDQ(71:0) DQ(71:0) DQ(71:0) P_CLK DCLKout CLK(3:0) CLK(3:0) DCLKin SDRAM SDRAM DIMM0 DIMM1 A4662-02 ® Affected
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Internal Bus IB Master/Slave IB Master/Slave PCI Master/Slave PCI Master/Slave Primary PCI Secondary PCI Documentation Changes 5. Figure 15-2 on pg 15-3 did not print correctly Problem: Figure 15-2 on pg 15-3 did not print correctly. Workaround: Replace Figure 15-2 with the following: Primary ATU P_ORQ 16 Bytes P_OWQ 16 Bytes P_OTQ P_IWQAD P_IWQ 256 Bytes P_IRQ 256 Bytes P_ITQ1 P_ITQ2 P_IDWQ 8 Bytes PCI-to-PCI Secondary ATU Bridge S_ORQ 16 Bytes S_OWQ 16 Bytes S_OTQ S_IWQAD S_IWQ 256 Byt
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Documentation Changes 6. Incorrect Vendor ID in ATU register Problem: The value for the Vendor ID register (ATUVID) is incorrect. Workaround: Replace Table 15-28 on page 15-60 with the following table: 15 12 8 4 0 IOP rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Attributes PCI ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro Attributes ® ® Attribute Legend: RW = Read/Write Intel i960 Core Local Bus Address PCI Configuration Address Offset RV = Reserved RC = Read Clear 1200H 00H - 01H PR = Pre
