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STK14D88
32Kx8 AutoStore™ nvSRAM
Features Description
■ 25, 35, 45 ns Read Access and R/W Cycle Time The Cypress STK14D88 is a 256Kb fast static RAM with a
nonvolatile Quantum Trap™ storage element included with each
■ Unlimited Read/Write Endurance
memory cell.
■ Automatic Nonvolatile STORE on Power Loss
The SRAM provides fast access and cycle times, ease of use,
and unlimited read and write endurance of a normal SRAM.
■ Nonvolatile STORE Under Hardware or Software Control
Data transfers auto
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STK14D88 Pin Configurations Figure 1. Pin Diagram 48-Pin SSOP/32-SOIC 32-SOIC 48-Pin SSOP V CAP 1 V 48 CC V CAP 1 32 VCC NC NC 2 47 A 14 2 31 HSB A 14 3 46 HSB A 3 30 12 W A 12 4 45 W A 7 4 29 A 13 A 7 A 44 13 5 A 6 28 A 5 8 A A 6 43 8 6 A A 5 27 9 6 A A 5 9 7 42 A 26 A 4 7 11 NC NC 41 8 A 25 3 8 G TOP A 4 40 A 9 11 NC 24 NC 9 NC 10 39 NC A 23 2 10 A 10 NC 38 11 NC A 1 11 22 E NC A 12 37 0 NC 12 21 DQ 7 TOP V SS 36 DQ DQ 13 V 0 13 20 6 SS 35 DQ NC 14 NC 1 19 DQ 14 5 NC 15 34 N
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STK14D88 Absolute Maximum Ratings Voltage on Input Relative to Ground.................–0.5V to 4.1V Note: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Voltage on Input Relative to V ...........–0.6V to (V + 0.5V) SS CC This is a stress rating only, and functional operation of the device Voltage on DQ or HSB ......................–0.5V to (V + 0.5V) 0-7 CC at conditions above those indicated in the operational sections of this spec
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STK14D88 DC Characteristics (continued) (V = 2.7V-3.6V) CC Commercial Industrial [2] Symbol Parameter Unit Notes Min Max Min Max V Output Logic “0” Voltage 0.4 0.4 V I = 4mA OL OUT T Operating Temperature 0 70 -40 85 °C A V Operating Voltage 2.7 3.6 2.7 3.6 V 3.3V +20%, -10% CC V Storage Capacitance 17 120 17 120 μFBetween V pin and V , 5V CAP CAP SS Rated DATA Data Retention 20 20 K R NV Nonvolatile STORE Operations 200 200 Years @ 55°C C AC Test Conditions Input Pulse Levels.................
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STK14D88 SRAM READ Cycles #1 and #2 Symbols STK14D88-25 STK14D88-35 STK14D88-45 NO. Parameter Unit #1 #2 Alt. Min Max Min Max Min Max 1t t Chip Enable Access Time 25 35 45 ns ELQV ACS [4] [4] 2t t t Read Cycle Time 25 35 45 ns AVAV ELEH RC [5] [5] 3t t t Address Access Time 25 35 45 ns AVQV AVQV AA 4t t Output Enable to Data Valid 12 15 20 ns GLQV OE [5] [5] 5t t t Output Hold after Address Change 3 3 3 ns AXQX AXQX OH 6t t Address Change or Chip Enable to 33 3 ns ELQX LZ Output Active [6] 7t t
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STK14D88 SRAM WRITE Cycle #1 and #2 Symbols STK14D88-25 STK14D88-35 STK14D88-45 NO. Parameter Unit #1 #2 Alt. Min Max Min Max Min Max 12 t t t Write Cycle Time 25 35 45 ns AVAV AVAV WC 13 t t t Write Pulse Width 20 25 30 ns WLWH WLEH WP 14 t t t Chip Enable to End of Write 20 25 30 ns ELWH ELEH CW 15 t t t Data Set-up to End of Write 10 12 15 ns DVWH DVEH DW 16 t t t Data Hold after End of Write 0 0 0 ns WHDX EHDX DH 17 t t t Address Set-up to End of Write 20 25 30 ns AVWH AVEH AW 18 t t t Addr
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STK14D88 AutoStore/POWER UP RECALL STK14D88 No. Symbols Alt. Parameter Unit Notes Min Max 22 t Power up RECALL Duration 20 ms 10 RECALL 23 t t STORE Cycle Duration 12.5 ms 11, 12 STORE HLHZ 24 V Low Voltage Trigger Level 2.65 V SWITCH 25 V Vcc Rise Time 150 μs CCRISE Figure 8. AutoStore /POWER UP RECALL 22 23 23 22 22 Note: Read and Write cycles are ignored during STORE, RECALL, and while V is below V CC SWITCH Notes 10. t starts from the time V rises above V . HRECALL CC SWITCH 11. If an SRA
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STK14D88 [13, 14] Software-Controlled STORE/RECALL Cycle Symbols STK14D88-25 STK14D88-35 STK14D88-45 No. Parameter Unit Notes Alternate E Cont Min Max Min Max Min Max 26 t t STORE/RECALL Initiation Cycle Time 25 35 45 ns 14 AVAV RC 27 t Address Setup Time 0 0 0 ns t AS AVEL 28 t Clock Pulse Width 20 25 30 ns t CW ELEH 29 Address Hold Time 1 1 1 ns t EHAX 30 RECALL Duration 50 50 50 μs t RECALL [14] Figure 9. E and G Controlled Software STORE/RECALL Cycle 26 26 t t AVAV AVAV ADDRESS ADDRESS #1
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STK14D88 Hardware STORE Cycle Symbols STK14D88 NO. Parameter Unit Notes Standard Alternate Min Max 31 t t Hardware STORE to SRAM Disabled 1 70 µs 15 DELAY HLQZ 32 t Hardware STORE Pulse Width 15 ns HLHX Figure 10. Hardware STORE Cycle 32 23 31 Soft Sequence Commands Symbols STK14D88 NO. Parameter Unit Notes Standard Min Max 33 t Soft Sequence Processing Time 70 µs 16, 17 SS Figure 11. Software Sequence Commands 33 33 Notes 15. Read and Write cycles in progress before HSB is asserted are given
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STK14D88 Mode Selection E W G A –A Mode IO Power Notes 14 0 H X X X Not Selected Output High Z Standby L H L X Read SRAM Output Data Active L L X X Write SRAM Input Data Active L H L 0x0E38 Read SRAM Output Data Active 18, 19, 20 0x31C7 Read SRAM Output Data 0x03E0 Read SRAM Output Data 0x3C1F Read SRAM Output Data 0x303F Read SRAM Output Data 0x03F8 AutoStore Disable Output Data L H L 0x0E38 Read SRAM Output Data Active 18, 19, 20 0x31C7 Read SRAM Output Data 0x03E0 Read SRAM Output Data 0x3C1F
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STK14D88 V pin is driven to 5V by a charge pump internal to the chip. A nvSRAM Operation CAP pull up should be placed on W to hold it inactive during power up. nvSRAM To reduce unneeded nonvolatile stores, AutoStore and Hardware Store operations will be ignored unless at least one The STK14D88 nvSRAM is made up of two functional compo- WRITE operation has taken place since the most recent STORE nents paired in the same physical cell. These are the SRAM or RECALL cycle. Software initiated STORE c
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STK14D88 To initiate the software STORE cycle, the following READ ■ The nonvolatile cells in an nvSRAM are programmed on the sequence must be performed: test floor during final test and quality assurance. Incoming inspection routines at customer or contract manufacturer’s 1. Read Address 0x0E38, Valid READ sites will sometimes reprogram these values. Final NV patterns 2. Read Address 0x31C7, Valid READ are typically repeating patterns of AA, 55, 00, FF, A5, or 5A. 3. Read Address 0x03E0, Va
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STK14D88 Figure 13. Current versus Cycle Time Preventing AutoStore The AutoStore function can be disabled by initiating an 50 AutoStore Disable sequence. A sequence of READ operations is performed in a manner similar to the software STORE initi- ation. To initiate the AutoStore Disable sequence, the following 40 sequence of E controlled or G controlled READ operations must be performed: 30 1. Read Address 0x0E38, Valid READ Writes 2. Read Address 0x31C7, Valid READ 20 3. Read Address 0x03E0, Va
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STK14D88 Part Numbering Nomenclature STK14D88 - R F 45 I TR Packaging Option: TR = Tape and Reel Blank = Tube Temperature Range: Blank - Commercial (0 to 70°C) I - Industrial (-40 to 85°C) Speed: 25 - 25 ns 35 - 35 ns 45 - 45 ns Lead Finish F = 100% Sn (Matte Tin) ROHS Compliant Package: N = Plastic 32-pin 300 mil SOIC (50 mil pitch) R = Plastic 48-pin 300 mil SSOP(25 mil pitch) Ordering Codes Part Number Description Access Times Temperature STK14D88-NF25 3V 32Kx8 AutoStore nvSRAM SOP32-300 25
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STK14D88 Package Diagrams Figure 14. 32-Pin (300 Mil) SOIC (51-85127) PIN 1 ID 16 1 MIN. DIMENSIONS IN INCHES[MM] 0.292[7.416] 0.299[7.594] MAX. 0.405[10.287] REFERENCE JEDEC MO-119 0.419[10.642] PART # 17 32 S32.3 STANDARD PKG. SZ32.3 LEAD FREE PKG. SEATING PLANE 0.810[20.574] 0.822[20.878] 0.090[2.286] 0.100[2.540] 0.004[0.101] 0.050[1.270] 0.006[0.152] 0.026[0.660] 0.021[0.533] TYP. 0.012[0.304] 0.032[0.812] 0.041[1.041] 0.004[0.101] 0.0100[0.254] 0.014[0.355] 0.020[0.508] 51-85127 *A Docume
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STK14D88 Package Diagrams (continued) Figure 15. 48-Pin (300 Mil) SSOP (51-85061) 51-85061-*C Document Number: 001-52037 Rev. ** Page 16 of 17 [+] Feedback
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STK14D88 Document History Page Document Title: STK14D88 32Kx8 AutoStore™ nvSRAM Document Number: 001-52037 Orig. of Submission Revision ECN Description of Change Change Date ** 2668632 GVCH 03/04/2009 New data sheet Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC Solution
