Bedienungsanleitung Cypress MoBL-USB CY7C68003

Inhaltszusammenfassung zur Seite Nr. 1

DATA BRIEF CY7C68003
MoBL-USB™ TX2UL USB 2.0
ULPI Transceiver
■ UART Pass Through Mode
Features
■ ESD Compliance:
™
The Cypress MoBL-USB TX2UL is a low voltage high speed
❐ JESD22-A114D 8 kV Contact Human Body Model (HBM) for
(HS) USB 2.0 ULPI Transceiver.
DP, DM, and VSS Pins
The TX2UL is specifically designed for mobile handset
❐ IEC61000-4-2 8 kV Contact Discharge
applications by offering tiny package options and low power
❐ IEC61000-4-2 15 kV Air Discharge
consumption.
■ Support for Indust

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CY7C68003 ■ Tri-state the ULPI bus output pins Functional Overview ■ Associate with RESET_N to place TX2UL in the Sleep mode UTMI+ Low Pin Interface (ULPI) When the CS_N pin is deasserted (high), all the pins in the ULPI This block conforms to the ULPI Specification. It supports the interface are tri-stated. 8-bit wide SDR data path. The primary IOs of this block support multi-range LVCMOS signaling from 1.8V to 3.3V (±5%). The USB2 Transceiver Macrocell Interface (UTMI+) level used is automatic

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CY7C68003 Clocking TX2UL supports external crystal and clock inputs at the 13, 19.2, The selection between input clock source and frequency on the 24, and 26 MHz frequencies. The internal PLL applies the proper XI pin is determined by the Chip Configuration register loaded clock multiply option depending on the input frequency. For appli- through the RESET_N during Configuration Mode. The external cations that use an external clock source to drive XI, the XO pin clock source requirements are s

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CY7C68003 Normal operation mode first, and then changes to Sleep mode. Operation Modes The Mode Change State diagram in Figure 3 shows the mode There are six operation modes available in TX2UL. They are: change path of TX2UL. The entries of the six operations modes (20-pin CSP package has 5 operation modes) are listed in ■ Normal Operation Mode Table 4 and Table 5. There are three mode change transactions ■ Configuration Mode that require the RESET_N assert or deassert with tSTATE (see Table 21

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CY7C68003 The operation and configuration modes are described in Sleep Mode Operation Modes on page 4 and Configuration Mode on page 14 Sleep mode is entered by asserting RESET_N during the Normal respectively. The ULPI Low power mode and Sleep mode are Operation Mode. When RESET_N is driven low for tSTATE (see described in the following sections: Table 21 on page 19 for tSTATE requirement) while CS_N is low, TX2UL enters into Sleep Mode. VCC must remain supplied (ON) ULPI Low Power Mode during