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CY7C1541V18, CY7C1556V18
CY7C1543V18, CY7C1545V18
72-Mbit QDR™-II+ SRAM 4-Word Burst
Architecture (2.0 Cycle Read Latency)
Features Configurations
■ Separate independent read and write data ports With Read Cycle Latency of 2.0 cycles:
❐ Supports concurrent transactions
CY7C1541V18 – 8M x 8
■ 375 MHz clock for high bandwidth
CY7C1556V18 – 8M x 9
CY7C1543V18 – 4M x 18
■ 4-word burst for reducing address bus frequency
CY7C1545V18 – 2M x 36
■ Double Data Rate (DDR) interfaces on both read and write
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2M x 8 Array 2M x 9 Array 2M x 8 Array 2M x 9 Array 2M x 8 Array 2M x 9 Array 2M x 8 Array 2M x 9 Array CY7C1541V18, CY7C1556V18 CY7C1543V18, CY7C1545V18 Logic Block Diagram (CY7C1541V18) 8 D [7:0] Write Write Write Write 21 Address A Reg Reg Reg Reg (20:0) Register 21 Address A (20:0) Register RPS K Control CLK K Logic Gen. DOFF Read Data Reg. CQ 32 V 16 REF 8 CQ Reg. Reg. Control 8 WPS Logic 8 16 8 Q NWS Reg. [7:0] [1:0] 8 QVLD Logic Block Diagram (CY7C1556V18) 9 D [8:0] Write Write Write Writ
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1M x 18 Array 512K x 36 Array 1M x 18 Array 512K x 36 Array 1M x 18 Array 512K x 36 Array 1M x 18 Array 512K x 36 Array CY7C1541V18, CY7C1556V18 CY7C1543V18, CY7C1545V18 Logic Block Diagram (CY7C1543V18) 18 D [17:0] Write Write Write Write 20 Address A Reg Reg Reg Reg (19:0) Register 20 Address A (19:0) Register RPS K Control CLK K Logic Gen. DOFF Read Data Reg. CQ 72 V 36 REF 18 CQ Reg. Reg. Control WPS 18 Logic 18 18 36 BWS Q Reg. [1:0] [17:0] 18 QVLD Logic Block Diagram (CY7C1545V18) 36 D [35
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CY7C1541V18, CY7C1556V18 CY7C1543V18, CY7C1545V18 Pin Configuration [2] The pin configuration for CY7C1541V18, CY7C1556V18, CY7C1543V18, and CY7C1545V18 follow. 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1541V18 (8M x 8) 1 2 3 4 5 6 7 8 9 10 11 A CQ AA WPS NWS K NC/144M RPS AA CQ 1 B NC NC NC A NC/288M K NWS ANC NC Q3 0 C NC NC NC V ANC A V NC NC D3 SS SS D NC D4 NC V V V V V NC NC NC SS SS SS SS SS E NC NC Q4 V V V V V NC D2 Q2 DDQ SS SS SS DDQ F NC NC NC V V V V V NC NC NC DDQ DD SS DD DDQ
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CY7C1541V18, CY7C1556V18 CY7C1543V18, CY7C1545V18 Pin Configuration (continued) [2] The pin configuration for CY7C1541V18, CY7C1556V18, CY7C1543V18, and CY7C1545V18 follow. 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1543V18 (4M x 18) 1 2 3 4 5 6 7 8 9 10 11 A CQ NC/144M A WPS BWS K NC/288M RPS AA CQ 1 B NC Q9 D9 A NC K BWS ANC NC Q8 0 C NC NC D10 V ANC A V NC Q7 D8 SS SS D NC D11 Q10 V V V V V NC NC D7 SS SS SS SS SS E NC NC Q11 V V V V V NC D6 Q6 DDQ SS SS SS DDQ F NC Q12 D12 V V V V V NC NC
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CY7C1541V18, CY7C1556V18 CY7C1543V18, CY7C1545V18 Pin Definitions Pin Name IO Pin Description D Input- Data Input Signals. Sampled on the rising edge of K and K clocks . when valid write operations are active [x:0] Synchronous CY7C1541V18 − D [7:0] CY7C1556V18 − D [8:0] CY7C1543V18 − D [17:0] CY7C1545V18 − D [35:0] WPS Input- Write Port Select − Active LOW. Sampled on the rising edge of the K clock. When asserted active, a Synchronous write operation is initiated. Deasserting deselects the wr
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CY7C1541V18, CY7C1556V18 CY7C1543V18, CY7C1545V18 Pin Definitions (continued) Pin Name IO Pin Description ZQ Input Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus impedance. CQ, CQ and Q output impedance are set to 0.2 x RQ, where RQ is a resistor connected [x:0] between ZQ and ground. Alternately, this pin can be connected directly to V , which enables the DDQ minimum impedance mode. This pin cannot be connected directly to GND or left
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CY7C1541V18, CY7C1556V18 CY7C1543V18, CY7C1545V18 seamless transition between devices without the insertion of wait Functional Overview states in a depth expanded memory. The CY7C1541V18, CY7C1556V18, CY7C1543V18, and Write Operations CY7C1545V18 are synchronous pipelined burst SRAMs equipped with a read port and a write port. The read port is Write operations are initiated by asserting WPS active at the dedicated to read operations and the write port is dedicated to rising edge of the positive
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CY7C1541V18, CY7C1556V18 CY7C1543V18, CY7C1545V18 Depth Expansion Valid Data Indicator (QVLD) The CY7C1543V18 has a port select input for each port. This QVLD is provided on the QDR-II+ to simplify data capture on high enables for easy depth expansion. Both port selects are sampled speed systems. The QVLD is generated by the QDR-II+ device on the rising edge of the positive input clock only (K). Each port along with data output. This signal is also edge-aligned with the select input can deselect
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CY7C1541V18, CY7C1556V18 CY7C1543V18, CY7C1545V18 [3, 4, 5, 6, 7, 8] The truth table for CY7C1541V18, CY7C1556V18, CY7C1543V18, and CY7C1545V18 follows. Truth Table Operation K RPS WPS DQ DQ DQ DQ [9] [10] Write Cycle: L-H H L D(A) at K(t + 1) ↑ D(A + 1) at K(t +1) ↑ D(A + 2) at K(t + 2) ↑ D(A + 3) at K(t + 2) ↑ Load address on the rising edge of K; input write data on two consecutive K and K rising edges. [10] Read Cycle: L-H L X Q(A) at K(t + 2) ↑ Q(A + 1) at K(t + 2) ↑ Q(A + 2) at K(t + 3)
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CY7C1541V18, CY7C1556V18 CY7C1543V18, CY7C1545V18 [3, 11] The write cycle description table for CY7C1556V18 follows. Write Cycle Descriptions BWS K K 0 L L–H – During the Data portion of a write sequence, the single byte (D ) is written into the device. [8:0] ) is written into the device. L – L–H During the Data portion of a write sequence, the single byte (D [8:0] H L–H – No data is written into the device during this portion of a write operation. H – L–H No data is written into the device dur
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CY7C1541V18, CY7C1556V18 CY7C1543V18, CY7C1545V18 Instruction Register IEEE 1149.1 Serial Boundary Scan (JTAG) Three-bit instructions can be serially loaded into the instruction These SRAMs incorporate a serial boundary scan Test Access register. This register is loaded when it is placed between the TDI Port (TAP) in the FBGA package. This part is fully compliant with and TDO pins, as shown in TAP Controller Block Diagram on IEEE Standard #1149.1-2001. The TAP operates using JEDEC page 15. Upon
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CY7C1541V18, CY7C1556V18 CY7C1543V18, CY7C1545V18 between the TDI and TDO pins and shifts the IDCODE out of the The shifting of data for the SAMPLE and PRELOAD phases can device when the TAP controller enters the Shift-DR state. The occur concurrently when required, that is, the data captured is IDCODE instruction is loaded into the instruction register at shifted out, the preloaded data can be shifted in. power up or whenever the TAP controller is supplied a BYPASS Test-Logic-Reset state. When
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CY7C1541V18, CY7C1556V18 CY7C1543V18, CY7C1545V18 [12] The state diagram for the TAP controller follows. TAP Controller State Diagram TEST-LOGIC 1 RESET 0 1 1 1 TEST-LOGIC/ SELECT SELECT 0 IDLE DR-SCAN IR-SCAN 0 0 1 1 CAPTURE-DR CAPTURE-IR 0 0 0 0 SHIFT-DR SHIFT-IR 1 1 1 1 EXIT1-DR EXIT1-IR 0 0 0 0 PAUSE-DR PAUSE-IR 1 1 0 0 EXIT2-DR EXIT2-IR 1 1 UPDATE-IR UPDATE-DR 1 1 0 0 Note 12. The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document Number: 001-05389 Rev. *
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CY7C1541V18, CY7C1556V18 CY7C1543V18, CY7C1545V18 TAP Controller Block Diagram 0 Bypass Register 2 1 0 Selection Selection TDI TDO Instruction Register Circuitry Circuitry 31 30 29 . . 2 1 0 Identification Register 108 . . . . 2 1 0 Boundary Scan Register TCK TAP Controller TMS TAP Electrical Characteristics [13, 14, 15] Over the Operating Range Parameter Description Test Conditions Min Max Unit Output HIGH Voltage I = −2.0 mA 1.4 V V OH1 OH V Output HIGH Voltage I = −100 μA1.6 V OH2 OH V Ou
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CY7C1541V18, CY7C1556V18 CY7C1543V18, CY7C1545V18 TAP AC Switching Characteristics [16, 17] Over the Operating Range Parameter Description Min Max Unit t TCK Clock Cycle Time 50 ns TCYC t TCK Clock Frequency 20 MHz TF t TCK Clock HIGH 20 ns TH t TCK Clock LOW 20 ns TL Setup Times t TMS Setup to TCK Clock Rise 5 ns TMSS t TDI Setup to TCK Clock Rise 5 ns TDIS t Capture Setup to TCK Rise 5 ns CS Hold Times t TMS Hold after TCK Clock Rise 5 ns TMSH t TDI Hold after Clock Rise 5 ns TDIH t Capture
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CY7C1541V18, CY7C1556V18 CY7C1543V18, CY7C1545V18 Identification Register Definitions Value Instruction Field Description CY7C1541V18 CY7C1556V18 CY7C1543V18 CY7C1545V18 Revision Number 000 000 000 000 Version number. (31:29) Cypress Device ID 11010010101000100 11010010101001100 11010010101010100 11010010101100100 Defines the type of (28:12) SRAM. Cypress JEDEC ID 00000110100 00000110100 00000110100 00000110100 Allows unique (11:1) identification of SRAM vendor. ID Register 1111 Indicates th
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CY7C1541V18, CY7C1556V18 CY7C1543V18, CY7C1545V18 Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID 0 6R 28 10G 56 6A 84 1J 1 6P29 9G 57 5B85 2J 2 6N 30 11F 58 5A 86 3K 3 7P 31 11G 59 4A 87 3J 4 7N32 9F 60 5C88 2K 5 7R 33 10F 61 4B 89 1K 6 8R 34 11E 62 3A 90 2L 7 8P 35 10E 63 2A 91 3L 8 9R 36 10D 64 1A 92 1M 9 11P 37 9E 65 2B 93 1L 10 10P 38 10C 66 3B 94 3N 11 10N 39 11D 67 1C 95 3M 12 9P 40 9C 68 1B 96 1N 13 10M 41 9D 69 3D 97 2M 14 11N 42 11B 70 3C 98 3P 15 9M 43 11C
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CY7C1541V18, CY7C1556V18 CY7C1543V18, CY7C1545V18 DLL Constraints Power Up Sequence in QDR-II+ SRAM ■ DLL uses K clock as its synchronizing input. The input must QDR-II+ SRAMs must be powered up and initialized in a have low phase jitter, which is specified as t . KC Var predefined manner to prevent undefined operations. During Power Up, when the DOFF is tied HIGH, the DLL gets locked ■ The DLL functions at frequencies down to 120 MHz. after 2048 cycles of stable clock. ■ If the input clock is
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CY7C1541V18, CY7C1556V18 CY7C1543V18, CY7C1545V18 Current into Outputs (LOW) ........................................ 20 mA Maximum Ratings Static Discharge Voltage (MIL-STD-883, M. 3015)... >2001V Exceeding maximum ratings may impair the useful life of the Latch-up Current .................................................... >200 mA device. These user guidelines are not tested. Storage Temperature ................................. –65°C to +150°C Operating Range Ambient Temperature with Power A
