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CY7C1480V25
CY7C1482V25
CY7C1486V25
72-Mbit (2M x 36/4M x 18/1M x 72)
Pipelined Sync SRAM
[1]
Features Functional Description
• Supports bus operation up to 250 MHz The CY7C1480V25/CY7C1482V25/CY7C1486V25 SRAM
integrates 2M x 36/4M x 18/1M × 72 SRAM cells with
• Available speed grades are 250, 200, and 167 MHz
advanced synchronous peripheral circuitry and a two-bit
• Registered inputs and outputs for pipelined operation
counter for internal burst operation. All synchronous inputs are
• 2.5V c
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CY7C1480V25 CY7C1482V25 CY7C1486V25 Logic Block Diagram – CY7C1480V25 (2M x 36) A 0, A1, A ADDRESS REGISTER 2 A [1:0] MODE ADV Q1 CLK BURST COUNTER AND CLR Q0 LOGIC ADSC ADSP DQD,DQP D DQ D ,DQPD BYTE BYTE BW D WRITE REGISTER WRITE DRIVER DQC,DQP C DQC,DQP C BYTE BYTE BW C OUTPUT WRITE DRIVER WRITE REGISTER OUTPUT MEMORY DQs SENSE BUFFERS ARRAY REGISTERS AMPS DQP A DQB,DQP B E DQB,DQP B DQP B BYTE BYTE BW B DQP C WRITE DRIVER WRITE REGISTER DQP D DQA,DQP A DQA,DQP A BYTE BW A BYTE WRITE DRIVER
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CY7C1480V25 CY7C1482V25 CY7C1486V25 Logic Block Diagram – CY7C1486V25 (1M x 72) ADDRESS A 0, A1,A REGISTER A[1:0] MODE ADV Q1 BINARY CLK COUNTER CLR Q0 ADSC ADSP DQ H, DQPH DQ H, DQPH BW H WRITE DRIVER WRITE DRIVER DQ G, DQPG DQ F, DQPF BW G WRITE DRIVER WRITE DRIVER DQ F, DQPF DQ F, DQPF BW F WRITE DRIVER WRITE DRIVER DQ E, DQPE DQ BYTE E, DQP “a” E BW E WRITE WRITE DRIVER DRIVER WRITE DRIVER MEMORY ARRAY DQ D, DQPD DQ D, DQPD BW D WRITE DRIVER WRITE DRIVER DQ C, DQPC DQ C, DQPC BW C WRITE DR
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CY7C1480V25 CY7C1482V25 CY7C1486V25 Pin Configurations 100-Pin TQFP Pinout DQP C 1 80 DQPB NC A 1 80 DQC DQB 2 79 NC 2 79 NC DQc DQB 3 78 NC 3 78 NC V DDQ V 4 77 V DDQ DDQ 4 77 V DDQ V V SSQ 5 76 V SSQ SSQ 5 76 V SSQ DQC DQB 6 75 NC 6 75 NC DQC 7 74 DQB NC DQPA 7 74 DQC 8 73 DQB DQB DQA 8 73 DQC 9 72 DQB DQB DQA 9 72 V SSQ 10 71 V V SSQ V SSQ 10 71 SSQ V DDQ V 11 70 V DDQ DDQ 11 70 V DDQ DQC DQB 12 69 DQB 12 69 DQA DQC DQB 13 68 DQB 13 68 DQA NC V 14 67 NC SS 14 67 V SS V DD 15 66 NC V DD 15
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CY7C1480V25 CY7C1482V25 CY7C1486V25 Pin Configurations (continued) 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1480V25 (2M x 36) 1 234 5 6 7 89 10 11 A A NC/288M CE BW BW CE NC A BWE ADSC ADV 1 C B 3 NC/144M CE2 BW BW NC/576M B A CLK GW OE ADSP A D A C DQP NC V V V V V V V NC/1G DQP C DDQ SS SS SS SS SS DDQ B D DQ DQ V V V V V V V DQ DQ C C DDQ DD SS SS SS DD DDQ B B E DQ DQ V V V V V V V DQ DQ C C DDQ DD SS SS SS DD DDQ B B DQ DQ V V V V V V V DQ DQ F C C DDQ DD SS SS SS DD DDQ B B DQ DQ
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CY7C1480V25 CY7C1482V25 CY7C1486V25 Pin Configurations (continued) 209-Ball FBGA (14 x 22 x 1.76 mm) Pinout CY7C1486V25 (1M × 72) 123456789 10 11 A DQ DQ G A CE ADSP ADSC ADV CE A DQ DQ G 2 B 3 B B DQ DQ G A G NC/288M BWE BWS DQ DQ BWS BWS BWS F B B C G B C DQ DQ NC/144M G NC/576M BWS BWS BWS CE BWS DQ G E DQ H D 1 A B B D DQ NC DQ V NC/1G OE GW V G G SS NC DQ SS DQ B B E DQP DQP V V V V V V V G C DDQ DDQ DD DD DD DDQ DDQ DQP DQP F B F DQ C DQ V V V NC V V DQ C V SS SS SS SS SS F DQ SS F G D
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CY7C1480V25 CY7C1482V25 CY7C1486V25 Pin Definitions Pin Name I/O Description A , A , A Input- Address Inputs used to select one of the address locations. Sampled at the rising 0 1 Synchronous edge of the CLK if ADSP or ADSC is active LOW, and CE , CE , and CE are sampled 1 2 3 active. A1: A0 are fed to the two-bit counter. Input- Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the BW , BW , BW , A B C Synchronous SRAM. Sampled on the rising edge of CLK.
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CY7C1480V25 CY7C1482V25 CY7C1486V25 Pin Definitions (continued) Pin Name I/O Description MODE Input Static Selects Burst Order. When tied to GND selects linear burst sequence. When tied to V DD or left floating selects interleaved burst sequence. This is a strap pin and must remain static during device operation. Mode pin has an internal pull up. TDO JTAG Serial Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the Output JTAG feature is not used, this pin m
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CY7C1480V25 CY7C1482V25 CY7C1486V25 DQs are automatically tri-stated whenever a write cycle is Sleep Mode detected, regardless of the state of OE. The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two Single Write Accesses Initiated by ADSC clock cycles are required to enter into or exit from this “sleep” ADSC Write accesses are initiated when the following condi- mode. While in this mode, data integrity is guaranteed. tions are satis
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CY7C1480V25 CY7C1482V25 CY7C1486V25 Truth Table [3, 4, 5, 6, 7] The truth table for CY7C1480V25, CY7C1482V25, and CY7C1486V25 follows. Operation Add. Used CE CE CE ZZ ADSP ADSC ADV WRITE OE CLK DQ 1 2 3 Deselect Cycle, Power Down None H X X L X L X X X L-H Tri-State Deselect Cycle, Power Down None L L X L L X X X X L-H Tri-State Deselect Cycle, Power Down None L X H L L X X X X L-H Tri-State Deselect Cycle, Power Down None L L X L H L X X X L-H Tri-State Deselect Cycle, Power Down None L X H
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CY7C1480V25 CY7C1482V25 CY7C1486V25 Truth Table for Read/Write [5] The read/write truth table for the CY7C1480V25 follows. Function GW BWE BW BW BW BW D C B A Read H H XXXX Read H L HHHH Write Byte A – (DQ and DQP) H L HHH L A A Write Byte B – (DQ and DQP)H L H H L H B B Write Bytes B, A H L H H L L Write Byte C – (DQ and DQP) H LH LH H C C Write Bytes C, A H L H L H L Write Bytes C, B H L H L L H Write Bytes C, B, A H L H L L L Write Byte D – (DQ and DQP) H L L HHH D D Write Bytes D, A H L L
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CY7C1480V25 CY7C1482V25 CY7C1486V25 Test Mode Select (TMS) IEEE 1149.1 Serial Boundary Scan (JTAG) The TMS input gives commands to the TAP controller and is The CY7C1480V25/CY7C1482V25/CY7C1486V25 incorpo- sampled on the rising edge of TCK. You can leave this ball rates a serial boundary scan test access port (TAP). This port unconnected if the TAP is not used. The ball is pulled up inter- operates in accordance with IEEE Standard 1149.1-1990 but nally, resulting in a logic HIGH level. does no
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CY7C1480V25 CY7C1482V25 CY7C1486V25 Instruction Register SAMPLE/PRELOAD; rather, it performs a capture of the IO ring when these instructions are executed. Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the Instructions are loaded into the TAP controller during the TDI and TDO balls as shown in the “TAP Controller Block Shift-IR state when the instruction register is placed between Diagram” on page 12. At power up,
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CY7C1480V25 CY7C1482V25 CY7C1486V25 The SRAM clock input might not be captured correctly if there BYPASS is no way in a design to stop (or slow) the clock during a When the BYPASS instruction is loaded in the instruction SAMPLE/PRELOAD instruction. If this is an issue, it is still register and the TAP is placed in a Shift-DR state, the bypass possible to capture all other signals and simply ignore the register is placed between the TDI and TDO balls. The value of the CLK captured in the bounda
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CY7C1480V25 CY7C1482V25 CY7C1486V25 2.5V TAP AC Test Conditions 1.8V TAP AC Test Conditions Input pulse levels ................................................ V to 2.5V Input pulse levels..................................... 0.2V to V – 0.2 SS DDQ Input rise and fall time..................................................... 1 ns Input rise and fall time .....................................................1 ns Input timing reference levels.........................................1.25V Input t
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CY7C1480V25 CY7C1482V25 CY7C1486V25 Scan Register Sizes Register Name Bit Size (x36) Bit Size (x18) Bit Size (x72) Instruction 3 3 3 Bypass 1 1 1 ID 32 32 32 Boundary Scan Order – 165FBGA 73 54 - Boundary Scan Order – 209BGA - - 112 Identification Codes Instruction Code Description EXTEST 000 Captures the IO ring contents. IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operations. SAMPLE Z 010 Captures
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CY7C1480V25 CY7C1482V25 CY7C1486V25 Boundary Scan Exit Order (4M x 18) Bit # 165-Ball ID Bit # 165-Ball ID Bit # 165-Ball ID 1D2 19 R8 37 C11 2E2 20 P3 38 A11 3F2 21 P4 39 A10 4G2 22 P8 40 B10 5J1 23 P9 41 A9 6 K1 24 P10 42 B9 7L1 25 R9 43 A8 8M1 26 R10 44 B8 9N1 27 R11 45 A7 10 R1 28 M10 46 B7 11 R2 29 L10 47 B6 12 R3 30 K10 48 A6 13 P2 31 J10 49 B5 14 R4 32 H11 50 A4 15 P6 33 G11 51 B3 16 R6 34 F11 52 A3 17 N6 35 E11 53 A2 18 P11 36 D11 54 B2 Document #: 38-05282 Rev. *H Page 17 of 32 [+] F
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CY7C1480V25 CY7C1482V25 CY7C1486V25 Boundary Scan Exit Order (1M x 72) Bit # 209-Ball ID Bit # 209-Ball ID Bit # 209-Ball ID Bit # 209-Ball ID 1 A1 29 T1 57 V10 85 C11 2A2 30 T2 58 U11 86 C10 3 B1 31 U1 59 U10 87 B11 4B2 32 U2 60 T11 88 B10 5 C1 33 V1 61 T10 89 A11 6C2 34 V2 62 R11 90 A10 7 D1 35 W1 63 R10 91 A9 8D2 36 W2 64 P11 92 U8 9 E1 37 T6 65 P10 93 A7 10 E2 38 V3 66 N11 94 A5 11 F1 39 V4 67 N10 95 A6 12 F2 40 U4 68 M11 96 D6 13 G1 41 W5 69 M10 97 B6 14 G2 42 V6 70 L11 98 D7 15 H1 43 W6
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CY7C1480V25 CY7C1482V25 CY7C1486V25 DC Input Voltage ................................... –0.5V to V + 0.5V Maximum Ratings DD Current into Outputs (LOW)......................................... 20 mA Exceeding the maximum ratings may impair the useful life of Static Discharge Voltage........................................... >2001V the device. These user guidelines are not tested. (MIL-STD-883, Method 3015) Storage Temperature .................................–65°C to +150°C Latch Up Current
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CY7C1480V25 CY7C1482V25 CY7C1486V25 [14] Capacitance 100 TQFP 165 FBGA 209 FBGA Parameter Description Test Conditions Unit Package Package Package C Address Input Capacitance T = 25°C, f = 1 MHz, 66 6 pF ADDRESS A V = 2.5V DD C Data Input Capacitance 5 5 5 pF DATA V = 2.5V DDQ C Control Input Capacitance 8 8 8 pF CTRL C Clock Input Capacitance 6 6 6 pF CLK C Input/Output Capacitance 5 5 5 pF I/O [14] Thermal Resistance 100 TQFP 165 FBGA 209 FBGA Parameter Description Test Conditions Unit Max.
