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CY7C1441AV33
CY7C1443AV33,CY7C1447AV33
36-Mbit (1M x 36/2M x 18/512K x 72)
Flow-Through SRAM
Features Functional Description
[1]
■ Supports 133-MHz bus operations The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33 are
3.3V, 1M x 36/2M x 18/512K x 72 Synchronous Flow-through
■ 1M x 36/2M x 18/512K x 72 common IO
SRAMs, respectively designed to interface with high-speed
microprocessors with minimum glue logic. Maximum access
■ 3.3V core power supply
delay from clock rise is 6.5 ns (133-MHz version). A
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CY7C1441AV33 CY7C1443AV33,CY7C1447AV33 Logic Block Diagram – CY7C1441AV33 (1M x 36) ADDRESS A 0, A1, A REGISTER A [1:0] MODE ADV Q1 BURST CLK COUNTER AND LOGIC Q0 CLR ADSC ADSP DQ D, DQP D DQ D, DQP D BYTE BW D BYTE BYTE WRITE REGISTER WRITE WRITE REGISTER REGISTER DQ C, DQP C DQ C, DQP C BYTE BW C BYTE WRITE REGISTER OUTPUT DQ s WRITE REGISTER MEMORY SENSE BUFFERS ARRAY DQP A DQ B, DQP B AMPS DQP B DQ B, DQP B BYTE BW B BYTE DQP C WRITE REGISTER DQP D WRITE REGISTER DQ A, DQP A BYTE DQ A, DQP
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CY7C1441AV33 CY7C1443AV33,CY7C1447AV33 Logic Block Diagram – CY7C1447AV33 (512K x 72) ADDRESS A 0, A1,A REGISTER A[1:0] MODE ADV Q1 BURST COUNTER CLK AND LOGIC CLR Q0 ADSC ADSP DQ H, DQPH DQ H, DQPH BW H WRITE REGISTER WRITE DRIVER DQ G, DQPG DQ F, DQPF BW G WRITE DRIVER WRITE REGISTER DQ F, DQPF DQ F, DQPF BW F WRITE DRIVER WRITE REGISTER DQ E, DQPE DQ E, DQPE BYTE “a” BW E WRITE DRIVER WRITE REGISTER WRITE DRIVER MEMORY ARRAY DQ D, DQPD DQ D, DQPD BW D WRITE REGISTER WRITE DRIVER DQ C, DQPC
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CY7C1441AV33 CY7C1443AV33,CY7C1447AV33 Pin Configurations Figure 1. 100-Pin TQFP Pinout DQP C DQP 1 80 NC B 1 80 A DQ C DQ 2 79 NC B 2 79 NC DQ DQ C 3 78 NC B 3 78 NC V DDQ 4 77 V DDQ V DDQ V 4 77 DDQ V SSQ 5 76 V SSQ V SSQ V 5 76 SSQ DQ C 6 75 DQ B NC NC 6 75 DQ C 7 74 DQ B NC DQP 7 74 A DQ C DQ 8 73 B DQ DQ B 8 73 A DQ C DQ 9 72 DQ B B 9 72 DQ A V SSQ V 10 71 V SSQ SSQ 10 71 V SSQ V DDQ V 11 70 V DDQ DDQ 11 70 V DDQ DQ C DQ 12 69 DQ B B 12 69 DQ A DQ C 13 68 DQ B DQ B 13 68 DQ A NC 14 67
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CY7C1441AV33 CY7C1443AV33,CY7C1447AV33 Pin Configurations (continued) 165-ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1441AV33 (1M x 36) 1 23 4 5 6 7 89 10 11 NC/288M CE BW BW CE BWE ADSC ADV A NC A A 3 1 C B NC/144M A CE BW BW CLK GW OE ADSP A NC/576M B 2 D A C DQP NC V V V V V V V NC/1G DQP C DDQ SS SS SS SS SS DDQ B DQ DQ V V V V V V V DQ DQ D C C DDQ DD SS SS SS DD DDQ B B DQ DQ V V V V V V V DQ DQ E C C DDQ DD SS SS SS DD DDQ B B F DQ DQ V V V V V V V DQ DQ C C DDQ DD SS SS SS DD DDQ B B G
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CY7C1441AV33 CY7C1443AV33,CY7C1447AV33 Pin Configurations (continued) 209-ball FBGA (14 x 22 x 1.76 mm) Pinout CY7C1447AV33 (512K × 72) 123456789 10 11 A DQ DQ A CE A DQ G ADSP ADSC ADV CE G 2 DQ 3 B B B DQ DQ G A BWS DQ G BWS BWS NC288M BW BWS DQ B C F B B G C DQ DQ NC/144M G NC/576M BWS DQ G BWS BWS CE BWS E DQ H D 1 A B B D DQ NC DQ V NC/1G OE GW G NC V G SS DQ SS DQ B B E DQP DQP V V V V V V V G C DDQ DDQ DDQ DDQ DD DD DD DQP DQP F B F DQ C DQ V V V DQ V V NC V C SS SS SS SS SS SS F DQ F
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CY7C1441AV33 CY7C1443AV33,CY7C1447AV33 Pin Definitions Name IO Description A , A , A Input- Address Inputs Used to Select One of the Address Locations. Sampled 0 1 Synchronous at the rising edge of the CLK if ADSP or ADSC is active LOW, and CE , CE , 1 2 and CE are sampled active. A feed the 2-bit counter. 3 [1:0] BW , BW Input- Byte Write Select Inputs, Active LOW. Qualified with BWE to conduct byte A B BW , BW , Synchronous writes to the SRAM. Sampled on the rising edge of CLK. C D BW
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CY7C1441AV33 CY7C1443AV33,CY7C1447AV33 Pin Definitions (continued) Name IO Description IO- Bidirectional Data IO lines. As inputs, they feed into an on-chip data register DQ s Synchronous that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the addresses presented during the previous clock rise of the read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HI
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CY7C1441AV33 CY7C1443AV33,CY7C1447AV33 Single Write Accesses Initiated by ADSC Functional Overview This write access is initiated when the following conditions are All synchronous inputs pass through input registers controlled by satisfied at clock rise: (1) CE , CE , and CE are all asserted 1 2 3 the rising edge of the clock. Maximum access delay from the active, (2) ADSC is asserted LOW, (3) ADSP is deasserted clock rise (t ) is 6.5 ns (133-MHz device). CDV HIGH, and (4) the write input sig
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CY7C1441AV33 CY7C1443AV33,CY7C1447AV33 ZZ Mode Electrical Characteristics Parameter Description Test Conditions Min. Max. Unit I Sleep mode standby current ZZ > V – 0.2V 100 mA DDZZ DD t Device operation to ZZ ZZ > V – 0.2V 2t ns ZZS DD CYC t ZZ recovery time ZZ < 0.2V 2t ns ZZREC CYC 2t t ZZ active to sleep current This parameter is sampled ns CYC ZZI t ZZ Inactive to exit sleep current This parameter is sampled 0 ns RZZI Truth Table [2, 3, 4, 5, 6] tThe truth table for CY7C1441AV33/CY7C1443A
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CY7C1441AV33 CY7C1443AV33,CY7C1447AV33 Partial Truth Table for Read/Write [2, 7] Function (CY7C1441AV33) GW BWE BW BW BW BW D C B A Read H H XXXX Read H L HHHH Write Byte A (DQ , DQP) H L HHH L A A Write Byte B(DQ , DQP)HLHHLH B B Write Bytes A, B (DQ , DQ , DQP , DQP)H L H H L L A B A B Write Byte C (DQ , DQP)HLHLHH C C Write Bytes C, A (DQ , DQ DQP , DQP)H L H L H L C A, C A Write Bytes C, B (DQ , DQ DQP , DQP)H L H L L H C B, C B Write Bytes C, B, A (DQ , DQ , DQ DQP , HLHL L L C B A, C DQP
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CY7C1441AV33 CY7C1443AV33,CY7C1447AV33 this ball unconnected if the TAP is not used. The ball is pulled up IEEE 1149.1 Serial Boundary Scan (JTAG) internally, resulting in a logic HIGH level. The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33 incor- Test Data-In (TDI) porates a serial boundary scan test access port (TAP). This part is fully compliant with 1149.1. The TAP operates using The TDI ball is used to serially input information into the registers JEDEC-standard 3.3V or 2.5V IO logic levels. an
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CY7C1441AV33 CY7C1443AV33,CY7C1447AV33 Instruction Register IDCODE Three-bit instructions can be serially loaded into the instruction The IDCODE instruction loads a vendor-specific, 32-bit code into register. This register is loaded when it is placed between the TDI the instruction register. It also places the instruction register and TDO balls as shown in the Tap Controller Block Diagram. between the TDI and TDO balls and shifts the IDCODE out of the Upon power up, the instruction register is
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CY7C1441AV33 CY7C1443AV33,CY7C1447AV33 EXTEST instruction. When HIGH, it enables the output buffers to drive the output bus. When LOW, this bit places the output bus into a The EXTEST instruction drives the preloaded data out through High-Z condition. the system output pins. This instruction also connects the boundary scan register for serial access between the TDI and This bit can be set by entering the SAMPLE/PRELOAD or TDO in the shift-DR controller state. EXTEST command, and then shifting
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CY7C1441AV33 CY7C1443AV33,CY7C1447AV33 TAP AC Switching Characteristics [9, 10] Over the Operating Range Parameter Description Min. Max. Unit Clock t TCK Clock Cycle Time 50 ns TCYC t TCK Clock Frequency 20 MHz TF t TCK Clock HIGH time 20 ns TH t TCK Clock LOW time 20 ns TL Output Times t TCK Clock LOW to TDO Valid 10 ns TDOV t TCK Clock LOW to TDO Invalid 0 ns TDOX Setup Times t TMS Setup to TCK Clock Rise 5 ns TMSS t TDI Setup to TCK Clock Rise 5 ns TDIS t Capture Setup to TCK Rise 5 ns CS
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CY7C1441AV33 CY7C1443AV33,CY7C1447AV33 3.3V TAP AC Test Conditions 2.5V TAP AC Test Conditions Input pulse levels.................................................V to 3.3V Input pulse levels.................................................V to 2.5V SS SS Input rise and fall times....................................................1 ns Input rise and fall time .....................................................1 ns Input timing reference levels........................................... 1.5V
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CY7C1441AV33 CY7C1443AV33,CY7C1447AV33 Identification Register Definitions CY7C1441AV33 CY7C1443AV33 CY7C1447AV33 Instruction Field Description (1M x 36) (2M x 18) (512K x 72) Revision Number (31:29) 000 000 000 Describes the version number. Device Depth (28:24) 01011 01011 01011 Reserved for Internal Use Architecture/Memory 000001 000001 000001 Defines memory type and architecture [12] Type(23:18) Bus Width/Density(17:12) 100111 010111 110111 Defines width and density Cypress JEDEC ID Code (1
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CY7C1441AV33 CY7C1443AV33,CY7C1447AV33 [13,14] 165-ball FBGA Boundary Scan Order CY7C1441AV33 (1M x 36), CY7C1443AV33 (2M x 18) Bit # Ball ID Bit # Ball ID Bit # Ball ID Bit # Ball ID 1 26 E11 51 A3 76 N1 N6 2 27 D11 52 A2 77 N2 N7 3 N10 28 G10 53B2 78P1 4P11 29 F10 54 C2 79 R1 5 P8 30 E10 55 B1 80 R2 6 R8 31 D10 56 A1 81 P3 7R9 32 C11 57 C1 82 R3 8P9 33 A11 58 D1 83 P2 9P10 34 B11 59E1 84 R4 10 R10 35 A10 60 F1 85 P4 11 R11 36 B10 61 G1 86 N5 12 H11 37 A9 62 D2 87 P6 13 N11 38 B9 63 E2 88 R6
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CY7C1441AV33 CY7C1443AV33,CY7C1447AV33 DC Input Voltage ................................... –0.5V to V + 0.5V Maximum Ratings DD Current into Outputs (LOW)......................................... 20 mA Exceeding maximum ratings may shorten the useful life of the Static Discharge Voltage........................................... >2001V device. User guidelines are not tested. (per MIL-STD-883, Method 3015) Storage Temperature ................................. –65°C to +150°C Latch-up Current..
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CY7C1441AV33 CY7C1443AV33,CY7C1447AV33 Capacitance [17] 100 TQFP 165 FBGA 209 FBGA Parameter Description Test Conditions Unit Max. Max. Max. C Input Capacitance T = 25°C, f = 1 MHz, 6.5 7 5 pF IN A V = 3.3V DD C Clock Input Capacitance 3 7 5 pF CLK V = 2.5V DDQ C Input/Output Capacitance 5.5 6 7 pF IO Thermal Resistance 100 TQFP 165 FBGA 209 FBGA [17] Parameter Description Test Conditions Unit Package Package Package Θ Thermal Resistance Test conditions follow standard 25.21 20.8 25.31 °C/W J
