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PRELIMINARY CY7C1333H
2-Mbit (64K x 32) Flow-Through SRAM
with NoBL™ Architecture
• Low standby power
Features
[1]
Functional Description
• Can support up to 133-MHz bus operations with zero
wait states.
The CY7C1333H is a 3.3V, 64K x 32 Synchronous
— Data is transferred on every clock.
Flow-through Burst SRAM designed specifically to support
• Pin compatible and functionally equivalent to ZBT™ unlimited true back-to-back Read/Write operations without the
devices insertion of wait states. The
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CY7C1333H PRELIMINARY Selection Guide CY7C1333H-133 CY7C1333H-100 Unit Maximum Access Time 6.5 8.0 ns Maximum Operating Current 225 205 mA Maximum CMOS Standby Current 40 40 mA Shaded area contains advance information. Please contact your local Cypress sales representative for availability of this part. Pin Configurations 100-lead TQFP NC 80 1 NC DQ 79 2 DQ C B DQ 78 C 3 DQ B V 77 4 DDQ V DDQ V 76 SS 5 V SS DQ 75 6 DQ C B DQ 74 C 7 DQ B BYTE B BYTE C DQ 73 8 DQ C B DQ 72 9 C DQ B V 71 10 V S
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CY7C1333H PRELIMINARY Pin Definitions (100-pin TQFP Package) Name I/O Description A , A , A Input- Address Inputs used to select one of the 64K address locations. Sampled at the rising edge 0 1 Synchronous of the CLK. A are fed to the two-bit burst counter. [1:0] Input- Byte Write Inputs, active LOW. Qualified with WE to conduct Writes to the SRAM. Sampled on BW [A:D] Synchronous the rising edge of CLK. Input- Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is activ
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CY7C1333H PRELIMINARY beginning of a burst cycle. Therefore, the type of access (Read Functional Overview or Write) is maintained throughout the burst sequence. The CY7C1333H is a synchronous flow-through burst SRAM Single Write Accesses designed specifically to eliminate wait states during Write-Read transitions. All synchronous inputs pass through Write access are initiated when the following conditions are input registers controlled by the rising edge of the clock. The satisfied at clock rise
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CY7C1333H PRELIMINARY Interleaved Burst Sequence Linear Burst Address Table (MODE = GND) First Second Third Fourth First Second Third Fourth Address Address Address Address Address Address Address Address A1, A0 A1, A0 A1, A0 A1, A0 A1, A0 A1, A0 A1, A0 A1, A0 00 01 10 11 00 01 10 11 01 10 11 00 01 00 11 10 10 11 00 01 10 11 00 01 11 00 01 10 11 10 01 00 ZZ Mode Electrical Characteristics Parameter Description Test Conditions Min. Max. Unit I Sleep mode standby current ZZ > V − 0.2V 40 mA DDZ
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CY7C1333H PRELIMINARY [2, 3] Truth Table for Read/Write Function BW BW BW BW WE A B C D Read H XXXX Write No Bytes Written L HHHH Write Byte A – (DQ) L L HHH A Write Byte B – (DQ)LHLHH B Write Byte C – (DQ)LHHLH C Write Byte D – (DQ) L HHH L D Write All Bytes L L L L L Document #: 001-00209 Rev. ** Page 6 of 12 [+] Feedback
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CY7C1333H PRELIMINARY Current into Outputs (LOW)......................................... 20 mA Maximum Ratings Static Discharge Voltage.......................................... > 2001V (Above which the useful life may be impaired. For user guide- (per MIL-STD-883, Method 3015) lines, not tested.) Latch-up Current.................................................... > 200 mA Storage Temperature .................................–65°C to +150°C Operating Range Ambient Temperature with Power Applie
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CY7C1333H PRELIMINARY [11] Capacitance Parameter Description Test Conditions 100 TQFP Package Unit C Input Capacitance T = 25°C, f = 1 MHz, 5pF IN A V = 3.3V DD C Clock Input Capacitance 5 pF CLOCK V =3.3V DDQ C I/O Capacitance 5 pF I/O AC Test Loads and Waveforms 3.3V I/O Test Load R = 317Ω 3.3V OUTPUT ALL INPUT PULSES V DDQ OUTPUT 90% Z = 50Ω 90% 0 R = 50Ω 10% 10% L GND 5pF R = 351Ω ≤ 1 ns ≤ 1 ns V = 1.5V L INCLUDING JIG AND (c) (a) (b) SCOPE [12, 13] Switching Characteristics Over the Operat
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CY7C1333H PRELIMINARY [12, 13] Switching Characteristics Over the Operating Range (continued) 133 MHz 100 MHz Parameter Description Min. Max. Min. Max. Unit Hold Times t Address Hold after CLK Rise 0.5 0.5 ns AH t ADV/LD Hold after CLK Rise 0.5 0.5 ns ALH t WE, BW Hold after CLK Rise 0.5 0.5 ns WEH [A:D] t CEN Hold after CLK Rise 0.5 0.5 ns CENH t Data Input Hold after CLK Rise 0.5 0.5 ns DH t Chip Enable Hold after CLK Rise 0.5 0.5 ns CEH Switching Waveforms [18, 19, 20] Read/Write Waveforms
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CY7C1333H PRELIMINARY Switching Waveforms (continued) [18, 19, 21] NOP, STALL and DESELECT Cycles 123 456 789 10 CLK CEN CE ADV/LD WE BW[A:B] ADDRESS A1 A2 A3 A4 A5 t CHZ DQ D(A1) Q(A2) Q(A3) D(A4) Q(A5) t DOH COMMAND WRITE READ STALL READ WRITE STALL NOP READ DESELECT CONTINUE D(A1) Q(A2) Q(A3) D(A4) Q(A5) DESELECT DON’T CARE UNDEFINED [22, 23] ZZ Mode Timing CLK t t ZZ ZZREC ZZ t ZZI I SUPPLY I DDZZ t RZZI ALL INPUTS DESELECT or READ Only (except ZZ) Outputs (Q) High-Z DON’T CARE Ordering Inf
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PRELIMINARY CY7C1333H Package Diagram 100-lead Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101 51-85050-*A NoBL and No Bus Latency are trademarks of Cypress Semiconductor. ZBT is a trademark of Integrated Device Technology. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 001-00209 Rev. ** Page 11 of 12 © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress
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CY7C1333H PRELIMINARY Document History Page Document Title: CY7C1333H 2-Mbit (64K x 32) Flow-Through SRAM with NoBL™ Architecture Document Number: 001-00209 Orig. of REV. ECN NO. Issue Date Change Description of Change ** 347377 See ECN PCI New Datasheet Document #: 001-00209 Rev. ** Page 12 of 12 [+] Feedback
