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CY7C1316BV18, CY7C1916BV18
CY7C1318BV18, CY7C1320BV18
18-Mbit DDR-II SRAM 2-Word
Burst Architecture
Features Functional Description
■ 18-Mbit density (2M x 8, 2M x 9, 1M x 18, 512K x 36) The CY7C1316BV18, CY7C1916BV18, CY7C1318BV18, and
CY7C1320BV18 are 1.8V Synchronous Pipelined SRAMs
■ 300 MHz clock for high bandwidth
equipped with DDR-II architecture. The DDR-II consists of an
SRAM core with advanced synchronous peripheral circuitry and
■ 2-word burst for reducing address bus frequency
a one
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1M x 8 Array 1M x 9 Array 1M x 8 Array 1M x 9 Array CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 Logic Block Diagram (CY7C1316BV18) Write Write 20 A Reg Reg (19:0) Address Register 8 LD K Output CLK R/W K Logic Gen. Control C DOFF Read Data Reg. C 16 CQ V 8 REF 8 Reg. Reg. Control CQ R/W Logic 8 8 NWS [1:0] Reg. 8 DQ [7:0] Logic Block Diagram (CY7C1916BV18) Write Write 20 A Reg Reg (19:0) Address Register 9 LD K Output CLK R/W K Logic Gen. Control C DOFF Read Data Reg. C 18 CQ V 9 REF 9
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512K x 18 Array 256K x 36 Array 512K x 18 Array 256K x 36 Array CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 Logic Block Diagram (CY7C1318BV18) Burst A0 Logic Write Write 20 19 A Reg Reg (19:0) A Address (19:1) Register 18 LD K Output CLK R/W K Logic Gen. Control C DOFF Read Data Reg. C 36 CQ V 18 REF 18 Reg. Reg. Control CQ R/W Logic 18 18 BWS [1:0] Reg. 18 DQ [17:0] Logic Block Diagram (CY7C1320BV18) Burst A0 Logic Write Write 19 18 A Reg Reg (18:0) A Address (18:1) Register 36 LD K O
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CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 Pin Configuration [1] The pin configuration for CY7C1316BV18, CY7C1916BV18, CY7C1318BV18, and CY7C1320BV18 follow. 165-Ball FBGA (13 x 15 x 1.4 mm) Pinout CY7C1316BV18 (2M x 8) 1 2 3 4 5 6 7 8 9 10 11 A CQ NC/72M A R/W NWS K NC/144M LD A NC/36M CQ 1 B NC NC NC A NC/288M K NWS ANC NC DQ3 0 C NC NC NC V AAA V NC NC NC SS SS D NC NC NC V V V V V NC NC NC SS SS SS SS SS E NC NC DQ4 V V V V V NC NC DQ2 DDQ SS SS SS DDQ F NC NC NC V V V V V NC N
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CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 Pin Configuration (continued) [1] The pin configuration for CY7C1316BV18, CY7C1916BV18, CY7C1318BV18, and CY7C1320BV18 follow. 165-Ball FBGA (13 x 15 x 1.4 mm) Pinout CY7C1318BV18 (1M x 18) 1 2 3 4 5 6 7 8 9 10 11 A CQ NC/72M A R/W BWS K NC/144M LD A NC/36M CQ 1 B NC DQ9 NC A NC/288M K BWS ANC NC DQ8 0 C NC NC NC V AA0A V NC DQ7 NC SS SS D NC NC DQ10 V V V V V NC NC NC SS SS SS SS SS E NC NC DQ11 V V V V V NC NC DQ6 DDQ SS SS SS DDQ F NC D
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CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 Pin Definitions Pin Name IO Pin Description DQ Input Output- Data Input Output Signals. Inputs are sampled on the rising edge of K and K clocks during valid write [x:0] Synchronous operations. These pins drive out the requested data during a read operation. Valid data is driven out on the rising edge of both the C and C clocks during read operations or K and K when in single clock mode. When read access is deselected, Q are automatically
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CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 Pin Definitions (continued) Pin Name IO Pin Description CQ Output Clock CQ Referenced with Respect to C. This is a free running clock and is synchronized to the input clock for output data (C) of the DDR-II. In single clock mode, CQ is generated with respect to K. The timing for the echo clocks is shown in Switching Characteristics on page 23. CQ Output Clock CQ Referenced with Respect to C. This is a free running clock and is synchronized
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CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 mation presented to D is also stored into the write data Functional Overview [17:0] register, provided BWS are both asserted active. The 36 bits [1:0] of data are then written into the memory array at the specified The CY7C1316BV18, CY7C1916BV18, CY7C1318BV18, and location. Write accesses can be initiated on every rising edge of CY7C1320BV18 are synchronous pipelined Burst SRAMs the positive input clock (K). This pipelines the data flow such
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CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 is generated with Programmable Impedance CQ is generated with respect to K and CQ respect to K. The timing for the echo clocks is shown in Switching An external resistor, RQ, must be connected between the ZQ pin Characteristics on page 23. on the SRAM and V to enable the SRAM to adjust its output SS driver impedance. The value of RQ must be 5x the value of the DLL intended line impedance driven by the SRAM. The allowable These chips use a D
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CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 Truth Table [2, 3, 4, 5, 6, 7] The truth table for the CY7C1316BV18, CY7C1916BV18, CY7C1318BV18, and CY7C1320BV18 follows. Operation K LD R/W DQ DQ Write Cycle: L-H L L D(A1) at K(t + 1) ↑ D(A2) at K(t + 1) ↑ Load address; wait one cycle; input write data on consecutive K and K rising edges. Read Cycle: L-H L H Q(A1) at C(t + 1)↑ Q(A2) at C(t + 2) ↑ Load address; wait one and a half cycle; read data on consecutive C and C rising edges. NOP
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CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 Write Cycle Descriptions [2, 8] The write cycle description table for CY7C1916BV18 follows. BWS K K Comments 0 L L–H – During the data portion of a write sequence, the single byte (D ) is written into the device. [8:0] ) is written into the device. L – L–H During the data portion of a write sequence, the single byte (D [8:0] H L–H – No data is written into the device during this portion of a write operation. H – L–H No data is written into t
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CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 Instruction Register IEEE 1149.1 Serial Boundary Scan (JTAG) Three-bit instructions can be serially loaded into the instruction These SRAMs incorporate a serial boundary scan Test Access register. This register is loaded when it is placed between the TDI Port (TAP) in the FBGA package. This part is fully compliant with and TDO pins, as shown in TAP Controller Block Diagram on IEEE Standard #1149.1-1900. The TAP operates using JEDEC page 15. U
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CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 IDCODE PRELOAD places an initial data pattern at the latched parallel outputs of the boundary scan register cells before the selection The IDCODE instruction loads a vendor-specific, 32-bit code into of another boundary scan test operation. the instruction register. It also places the instruction register between the TDI and TDO pins and shifts the IDCODE out of the The shifting of data for the SAMPLE and PRELOAD phases can device when the TA
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CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 TAP Controller State Diagram [9] The state diagram for the TAP controller follows. TEST-LOGIC 1 RESET 0 1 1 1 TEST-LOGIC/ SELECT SELECT 0 IDLE DR-SCAN IR-SCAN 0 0 1 1 CAPTURE-DR CAPTURE-IR 0 0 0 0 SHIFT-DR SHIFT-IR 1 1 1 1 EXIT1-DR EXIT1-IR 0 0 0 0 PAUSE-DR PAUSE-IR 1 1 0 0 EXIT2-DR EXIT2-IR 1 1 UPDATE-IR UPDATE-DR 1 1 0 0 Note 9. The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document Number: 38-05621 Rev.
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CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 TAP Controller Block Diagram 0 Bypass Register 2 1 0 Selection Selection TDI TDO Instruction Register Circuitry Circuitry 31 30 29 . . 2 1 0 Identification Register . 106 . . . 2 1 0 Boundary Scan Register TCK TAP Controller TMS TAP Electrical Characteristics [10, 11, 12] Over the Operating Range Parameter Description Test Conditions Min Max Unit V Output HIGH Voltage I = −2.0 mA 1.4 V OH1 OH Output HIGH Voltage I = −100 μA1.6 V V OH2 OH
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CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 TAP AC Switching Characteristics [13, 14] Over the Operating Range Parameter Description Min Max Unit t TCK Clock Cycle Time 50 ns TCYC t TCK Clock Frequency 20 MHz TF t TCK Clock HIGH 20 ns TH t TCK Clock LOW 20 ns TL Setup Times t TMS Setup to TCK Clock Rise 5 ns TMSS t TDI Setup to TCK Clock Rise 5 ns TDIS t Capture Setup to TCK Rise 5 ns CS Hold Times t TMS Hold after TCK Clock Rise 5 ns TMSH t TDI Hold after Clock Rise 5 ns TDIH t Capt
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CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 Identification Register Definitions Value Instruction Field Description CY7C1316BV18 CY7C1916BV18 CY7C1318BV18 CY7C1320BV18 Revision Number 000 000 000 000 Version number. (31:29) Cypress Device ID 11010100010000101 11010100010001101 11010100010010101 11010100010100101 Defines the type of (28:12) SRAM. Cypress JEDEC ID 00000110100 00000110100 00000110100 00000110100 Allows unique (11:1) identification of SRAM vendor. ID Register 1111 Indi
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CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID 0 6R 27 11H 54 7B 81 3G 1 6P 28 10G 55 6B 82 2G 26N 29 9G 56 6A 83 1J 3 7P 30 11F 57 5B 84 2J 4 7N 31 11G 58 5A 85 3K 57R 32 9F 59 4A 86 3J 6 8R 33 10F 60 5C 87 2K 7 8P 34 11E 61 4B 88 1K 8 9R 35 10E 62 3A 89 2L 9 11P 36 10D 63 1H 90 3L 10 10P 37 9E 64 1A 91 1M 11 10N 38 10C 65 2B 92 1L 12 9P 39 11D 66 3B 93 3N 13 10M 40 9C 67 1C 94 3M 14 11N 41 9D 68 1B 95 1N 15 9M
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~ ~ CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 DLL Constraints Power Up Sequence in DDR-II SRAM ■ DLL uses K clock as its synchronizing input. The input must DDR-II SRAMs must be powered up and initialized in a have low phase jitter, which is specified as t . KC Var predefined manner to prevent undefined operations. ■ The DLL functions at frequencies down to 120 MHz. Power Up Sequence ■ If the input clock is unstable and the DLL is enabled, then the ■ Apply power and drive DOFF eith
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CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 Current into Outputs (LOW) ........................................ 20 mA Maximum Ratings Static Discharge Voltage (MIL-STD-883, M 3015).... >2001V Exceeding maximum ratings may impair the useful life of the Latch up Current..................................................... >200 mA device. These user guidelines are not tested. Storage Temperature ................................. –65°C to +150°C Operating Range Ambient Temperature with Pow
