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CY7C1305BV25 CY7C1307BV25 is loaded into the instruction register upon power-up or BYPASS whenever the TAP controller is given a test logic reset state. When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass SAMPLE Z register is placed between the TDI and TDO pins. The The SAMPLE Z instruction causes the boundary scan register advantage of the BYPASS instruction is that it shortens the to be connected between the TDI and TDO pins
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CY7C1305BV25 CY7C1307BV25 [11] TAP Controller State Diagram TEST-LOGIC 1 RESET 0 1 1 1 TEST-LOGIC/ SELECT SELECT 0 IDLE DR-SCAN IR-SCAN 0 0 1 1 CAPTURE-DR CAPTURE-IR 0 0 SHIFT-DR 0 SHIFT-IR 0 1 1 1 1 EXIT1-DR EXIT1-IR 0 0 0 0 PAUSE-DR PAUSE-IR 1 1 0 0 EXIT2-DR EXIT2-IR 1 1 UPDATE-DR UPDATE-IR 1 1 0 0 Note: 11. The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document #: 38-05630 Rev. *A Page 11 of 21 [+] Feedback
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CY7C1305BV25 CY7C1307BV25 TAP Controller Block Diagram 0 Bypass Register Selection Selection TDI 2 1 0 TDO Circuitry Circuitry Instruction Register 29 31 30 . . 2 1 0 Identification Register . 106 . . . 2 1 0 Boundary Scan Register TCK TAP Controller TMS [12, 15, 17] TAP Electrical Characteristics Over the Operating Range Parameter Description Test Conditions Min. Max. Unit V Output HIGH Voltage I = −2.0 mA 1.7 V OH1 OH V Output HIGH Voltage I = −100 µA2.1 V OH2 OH V Output LOW Voltage I =
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CY7C1305BV25 CY7C1307BV25 [13, 14] TAP AC Switching Characteristics Over the Operating Range (continued) Parameter Description Min. Max. Unit Output Times t TCK Clock LOW to TDO Valid 20 ns TDOV t TCK Clock LOW to TDO Invalid 0 ns TDOX [14] TAP Timing and Test Conditions 1.25V 50Ω ALL INPUT PULSES TDO 2.5V Z =50Ω 0 1.25V C = 20 pF L 0V t GND TL t (a) TH Test Clock TCK t TCYC t TMSS t TMSH Test Mode Select TMS t TDIS t TDIH Test Data-In TDI Test Data-Out TDO t t TDOX TDOV Identification Registe
Inhaltszusammenfassung zur Seite Nr. 14
CY7C1305BV25 CY7C1307BV25 Scan Register Sizes Register Name Bit Size Instruction 3 Bypass 1 ID 32 Boundary Scan 107 Instruction Codes Instruction Code Description EXTEST 000 Captures the Input/Output ring contents. IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operation. SAMPLE Z 010 Captures the Input/Output contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output driv
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CY7C1305BV25 CY7C1307BV25 Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID 0 6R 27 11H 54 7B 81 3G 1 6P 28 10G 55 6B 82 2G 2 6N 29 9G 56 6A 83 1J 3 7P 30 11F 57 5B 84 2J 4 7N 31 11G 58 5A 85 3K 5 7R 32 9F 59 4A 86 3J 6 8R 33 10F 60 5C 87 2K 7 8P 34 11E 61 4B 88 1K 8 9R 35 10E 62 3A 89 2L 9 11P 36 10D 63 1H 90 3L 10 10P 37 9E 64 1A 91 1M 11 10N 38 10C 65 2B 92 1L 12 9P 39 11D 66 3B 93 3N 13 10M 40 9C 67 1C 94 3M 14 11N 41 9D 68 1B 95 1N 15 9M 42 11B 69 3D 96 2M 16 9N
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CY7C1305BV25 CY7C1307BV25 Current into Outputs (LOW)......................................... 20 mA Maximum Ratings Static Discharge Voltage.......................................... > 2001V (Above which the useful life may be impaired.) (per MIL-STD-883, Method 3015) Storage Temperature ................................ –65°C to + 150°C Latch-Up Current................................................... > 200 mA Ambient Temperature with Power Applied...........................................
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CY7C1305BV25 CY7C1307BV25 [22] Capacitance Parameter Description Test Conditions Max. Unit C Input Capacitance T = 25°C, f = 1 MHz, 5pF IN A V = 2.5V. DD C Clock Input Capacitance 6 pF CLK V = 1.5V DDQ C Output Capacitance 7 pF O AC Test Loads and Waveforms V = 0.75V REF 0.75V V REF V REF 0.75V R = 50Ω OUTPUT [23] ALL INPUT PULSES Z = 50Ω 0 OUTPUT 1.25V Device R = 50Ω L 0.75V Under Device 0.25V Test 5pF Under V = 0.75V Slew Rate = 2 V/ns REF ZQ Test ZQ RQ = RQ = 250Ω 250Ω (a) (b) Docume
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CY7C1305BV25 CY7C1307BV25 [23] Switching Characteristics Over the Operating Range 167 MHz Cypress Consortium Parameter Parameter Description Min. Max. Unit [24] t V (typical) to the First Access Read or Write 10 µs Power CC Cycle Time t t K Clock and C Clock Cycle Time 6.0 ns CYC KHKH t t Input Clock (K/K and C/C) HIGH 2.4 ns KH KHKL t t Input Clock (K/K and C/C) LOW 2.4 ns KL KLKH t t K/K Clock Rise to K/K Clock Rise and C/C to C/C Rise (rising edge 2.7 3.3 ns KHKH KHKH to rising edge) t t K
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CY7C1305BV25 CY7C1307BV25 [27, 28, 29] Switching Waveforms NOP READ WRITE READ WRITE NOP 1 7 23456 K t t t t KH KL CYC KHKH K RPS t t t t SC HC HC SC WPS A A0 A1 A2 A3 t t HD HD t t SA HA t t SD SD D D10 D11 D12 D13 D30 D31 D32 D33 Q Qx3 Q00 Q01 Q02 Q03 Q20 Q21 Q22 Q23 t t KHCH CO t DOH t t CLZ CHZ t t CO DOH C t t t t KHCH CYC KH KL t KHKH C DON’T CARE UNDEFINED Notes: 27. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, i.e., A0+
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CY7C1305BV25 CY7C1307BV25 Ordering Information “Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered”. Speed Package Operating (MHz) Ordering Code Diagram Package Type Range 167 CY7C1305BV25-167BZC 51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Commercial CY7C1307BV25-167BZC CY7C1305BV25-167BZXC 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead free C
Inhaltszusammenfassung zur Seite Nr. 1
CY7C1305BV25
CY7C1307BV25
18-Mbit Burst of 4 Pipelined SRAM with
QDR™ Architecture
Features Functional Description
• Separate independent Read and Write data ports The CY7C1305BV25/CY7C1307BV25 are 2.5V Synchronous
Pipelined SRAMs equipped with QDR architecture. QDR
• Supports concurrent transactions
architecture consists of two separate ports to access the
• 167-MHz clock for high bandwidth
memory array. The Read port has dedicated Data Outputs to
support Read operations and the Write Port has
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256Kx18 Array 128K x 36 Array 256Kx18 Array 128K x 36 Array 256Kx18 Array 128K x 36 Array 256Kx18 Array 128K x 36 Array CY7C1305BV25 CY7C1307BV25 Logic Block Diagram (CY7C1305BV25) D [17:0] 18 Write Write Write Write Reg Reg Reg Reg Address Register A Address [17:0] A (17:0) 18 Register 18 K CLK K RPS Control Gen. Logic C Read Data Reg. C 72 36 Vref Reg. Reg. WPS 18 Control 36 BWS Logic [0:1] Reg. Q [17:0] 18 Logic Block Diagram (CY7C1307BV25) D [35:0] 36 Write Write Write Write Reg Reg Reg Re
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CY7C1305BV25 CY7C1307BV25 \ Pin Configuration 165-ball FBGA (13 x 15 x 1.4 mm) Pinout CY7C1305BV25 (1M x 18) 1 2 3 4 5 678 9 10 11 A NC GND/ 144M NC/ 36M WPS BWS K NC RPS A GND/ 72M NC 1 B NC Q9 D9 A NC K BWS ANC NC Q8 0 C NC NC D10 VSS A NC A VSS NC Q7 D8 D NC D11 Q10 VSS VSS VSS VSS VSS NC NC D7 E NC NC Q11 VDDQ VSS VSS VSS VDDQ NC D6 Q6 F NC Q12 D12 VDDQ VDD VSS VDD VDDQ NC NC Q5 G NC D13 Q13 VDDQ VDD VSS VDD VDDQ NC NC D5 H NC VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ J NC NC D14 VDDQ
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CY7C1305BV25 CY7C1307BV25 Pin Definitions Name I/O Description D Input- Data input signals, sampled on the rising edge of K and K clocks during valid write [x:0] Synchronous operations. CY7C1305BV25 – D [17:0] CY7C1307BV25 – D [35:0] WPS Input- Write Port Select, active LOW. Sampled on the rising edge of the K clock. When Synchronous asserted active, a Write operation is initiated. Deasserting will deselect the Write port. Deselecting the Write port will cause D to be ignored. [x:0] BWS ,
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CY7C1305BV25 CY7C1307BV25 Pin Definitions (continued) Name I/O Description NC/36M N/A Address expansion for 36M. This is not connected to the die. Can be connected to any voltage level on CY7C1305BV25/CY7C1307BV25. GND/72M Input Address expansion for 72M. This should be tied LOW on the CY7C1305BV25. NC/72M N/A Address expansion for 72M. This can be connected to any voltage level on CY7C1307BV25. GND/144M Input Address expansion for 144M. This should be tied LOW on CY7C1305BV25/CY7C1307BV25
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CY7C1305BV25 CY7C1307BV25 When deselected, the write port will ignore all inputs after the includes forwarding data from a Write cycle that was initiated pending Write operations have been completed. on the previous K clock rise. Read and Write accesses must be scheduled such that one Byte Write Operations transaction is initiated on any clock cycle. If both ports are Byte Write operations are supported by the CY7C1305BV25. selected on the same K clock rise, the arbitration depends on A write
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CY7C1305BV25 CY7C1307BV25 [2, 3, 4, 5, 6, 7, 8, 9] Truth Table Operation K RPS WPS DQ DQ DQ DQ [8] [9] Write Cycle: L-H H L D(A+00) at D(A+01) at D(A+10) at D(A+11) at Load address on the rising K(t+1) ↑ K(t+1) ↑ K(t+2) ↑ K(t+2) ↑ edge of K; wait one cycle; input write data on two consecutive K and K rising edges. [9] Read Cycle: L-H L X Q(A+00) at Q(A+01) at Q(A+10) at Q(A+11) at Load address on the rising C(t+1) ↑ C(t+1) ↑ C(t+2) ↑ C(t+2) ↑ edge of K; wait one cycle; read data on two
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CY7C1305BV25 CY7C1307BV25 [2, 10] Write Cycle Descriptions (CY7C1307BV25) BWS BWS BWS BWS KK Comments 0 1 2 3 L L L L L-H – During the Data portion of a Write sequence, all four bytes (D ) are written into the device. [35:0] L L L L – L-H During the Data portion of a Write sequence, all four bytes (D ) are written into the device. [35:0] L H H H L-H – During the Data portion of a Write sequence, only the lower byte (D ) is written into the device. D will remain [8:0] [35:9] unaltered. L
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CY7C1305BV25 CY7C1307BV25 TDI and TDO pins as shown in TAP Controller Block Diagram. IEEE 1149.1 Serial Boundary Scan (JTAG) Upon power-up, the instruction register is loaded with the These SRAMs incorporate a serial boundary scan test access IDCODE instruction. It is also loaded with the IDCODE port (TAP) in the FBGA package. This part is fully compliant instruction if the controller is placed in a reset state as with IEEE Standard #1149.1-1900. The TAP operates using described in the previou
