Inhaltszusammenfassung zur Seite Nr. 1
CY7C1161V18, CY7C1176V18
CY7C1163V18, CY7C1165V18
18-Mbit QDR™-II+ SRAM 4-Word Burst
Architecture (2.5 Cycle Read Latency)
Features Functional Description
■ Separate independent read and write data ports The CY7C1161V18, CY7C1176V18, CY7C1163V18, and
CY7C1165V18 are 1.8V Synchronous Pipelined SRAMs
❐ Supports concurrent transactions
equipped with QDR™-II+ architecture. QDR-II+ architecture
■ 300 MHz to 400 MHz clock for high bandwidth
consists of two separate ports to access the memory array. Th
Inhaltszusammenfassung zur Seite Nr. 2
512K x 8 Array 512K x 9 Array 512K x 8 Array 512K x 9 Array 512K x 8 Array 512K x 9 Array 512K x 8 Array 512K x 9 Array CY7C1161V18, CY7C1176V18 CY7C1163V18, CY7C1165V18 Logic Block Diagram (CY7C1161V18) D [7:0] 8 Write Write Write Write Address A Reg Reg Reg Reg (18:0) Address Register 19 Register A (18:0) 19 K RPS Control CLK K Logic Gen. DOFF Read Data Reg. CQ 32 CQ 16 V REF Reg. Reg. WPS Control Q [7:0] 16 Logic NWS [1:0] Reg. 8 8 QVLD Logic Block Diagram (CY7C1176V18) D [8:0] 9 Write Write
Inhaltszusammenfassung zur Seite Nr. 3
256K x 18 Array 128K x 36 Array 256K x 18 Array 128K x 36 Array 256K x 18 Array 128K x 36 Array 256K x 18 Array 128K x 36 Array CY7C1161V18, CY7C1176V18 CY7C1163V18, CY7C1165V18 Logic Block Diagram (CY7C1163V18) D [17:0] 18 Write Write Write Write Address A Reg Reg Reg (17:0) Reg Register 18 Address Register A (17:0) 18 RPS K Control CLK K Logic Gen. DOFF Read Data Reg. CQ 72 CQ 36 V REF Reg. Reg. WPS Control Q [17:0] Logic 36 BWS [1:0] Reg. 18 18 QVLD Logic Block Diagram (CY7C1165V18) D [35:0]
Inhaltszusammenfassung zur Seite Nr. 4
CY7C1161V18, CY7C1176V18 CY7C1163V18, CY7C1165V18 Pin Configurations 165-Ball FBGA (13 x 15 x 1.4 mm) Pinout CY7C1161V18 (2M x 8) 1 23 5 6 7 8 910 11 4 NC/72M A K NC/ NC/14 144M 4M ANC/36M CQ A CQ WPS NWS RPS 1 NC NC NC A NC/288M K NWS A NC NC Q3 B 0 C NC NC NC V ANCA V NC NC D3 SS SS NC D4 NC V V V V V NC NC NC D SS SS SS SS SS NC NC Q4 V V V V V NC D2 Q2 E DDQ SS SS SS DDQ F NC NC NC V V V V V NC NC NC DDQ DD SS DD DDQ G NC D5 Q5 V V V V V NC NC NC DDQ DD SS DD DDQ V V V V V V V V V ZQ H REF
Inhaltszusammenfassung zur Seite Nr. 5
CY7C1161V18, CY7C1176V18 CY7C1163V18, CY7C1165V18 Pin Configurations (continued) 165-Ball FBGA (13 x 15 x 1.4 mm) Pinout CY7C1163V18 (1M x 18) 1 23 4 56 7 8 910 11 CQ NC/144M NC/36M WPS BWS K NC/288M RPS ANC/72M CQ A 1 NC Q9 D9 A NC K BWS A NC NC Q8 B 0 C NC NC D10 V ANCA V NC Q7 D8 SS SS NC D11 V V V V NC D7 D Q10 V NC SS SS SS SS SS NC NC Q11 V V V V V NC D6 Q6 E DDQ SS SS SS DDQ F NC Q12 D12 V V V V V NC NC Q5 DDQ DD SS DD DDQ G NC D13 Q13 V V V V V NC NC D5 DDQ DD SS DD DDQ V H DOFF V V V V
Inhaltszusammenfassung zur Seite Nr. 6
CY7C1161V18, CY7C1176V18 CY7C1163V18, CY7C1165V18 Pin Definitions Pin Name IO Pin Description D Input- Data Input Signals. Sampled on the rising edge of K and K clocks during valid write operations. [x:0] Synchronous CY7C1161V18−D [7:0] CY7C1176V18−D [8:0] CY7C1163V18−D [17:0] CY7C1165V18−D [35:0] WPS Input- Write Port Select − Active LOW. Sampled on the rising edge of the K clock. When asserted active, Synchronous a write operation is initiated. Deasserting deselects the write port. Deselecti
Inhaltszusammenfassung zur Seite Nr. 7
CY7C1161V18, CY7C1176V18 CY7C1163V18, CY7C1165V18 Pin Definitions (continued) Pin Name IO Pin Description CQ Echo Clock Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input clock (K) of the QDR-II+. The timings for the echo clocks are shown in “Switching Characteristics” on page 23. ZQ Input Output Impedance Matching Input. Used to tune the device outputs to the system data bus impedance. CQ, CQ and Q output impedance are set to 0.2 x RQ, where RQ is a
Inhaltszusammenfassung zur Seite Nr. 8
CY7C1161V18, CY7C1176V18 CY7C1163V18, CY7C1165V18 Write Operations Functional Overview Write operations are initiated by asserting WPS active at the The CY7C1161V18, CY7C1176V18, CY7C1163V18, and rising edge of the positive input clock (K). On the following K CY7C1165V18 are synchronous pipelined burst SRAMs clock rise, the data presented to D is latched and stored into [17:0] equipped with both a read port and a write port. The read port is the lower 18-bit write data register, provided BWS are
Inhaltszusammenfassung zur Seite Nr. 9
CY7C1161V18, CY7C1176V18 CY7C1163V18, CY7C1165V18 Depth Expansion Valid Data Indicator (QVLD) The CY7C1163V18 has a port select input for each port. This QVLD is provided on the QDR-II+ to simplify data capture on high enables easy depth expansion. Both port selects are only speed systems. The QVLD is generated by the QDR-II+ device sampled on the rising edge of the positive input clock (K). Each along with data output. This signal is also edge-aligned with the port select input can deselect the
Inhaltszusammenfassung zur Seite Nr. 10
CY7C1161V18, CY7C1176V18 CY7C1163V18, CY7C1165V18 Application Example Figure 1 shows four QDR-II+ used in an application. Figure 1. Application Example RQ = 250ohms RQ = 250ohms ZQ ZQ CQ/CQ Vt SRAM #1 CQ/CQ SRAM #4 Q D D Q R BWS K A RPS WPS K A K K RPS WPS BWS DATA IN R DATA OUT Vt Address Vt R RPS BUS MASTER WPS (CPU or ASIC) BWS CLKIN/CLKIN Source K Source K R = 50ohms, Vt = V /2 DDQ Truth Table [3, 4, 5, 6, 7, 8] The truth table for the CY7C1161V18, CY7C1176V18, CY7C1163V18, and CY7C
Inhaltszusammenfassung zur Seite Nr. 11
CY7C1161V18, CY7C1176V18 CY7C1163V18, CY7C1165V18 Write Cycle Descriptions [3, 11] The write cycle descriptions of CY7C1161V18 and CY7C1163V18 follow. BWS / BWS / 0 1 K Comments K NWS NWS 0 1 L L L–H – During the data portion of a write sequence: CY7C1161V18 − both nibbles (D ) are written into the device. [7:0] CY7C1163V18 − both bytes (D ) are written into the device. [17:0] L L – L-H During the data portion of a write sequence: CY7C1161V18 − both nibbles (D ) are written into the device. [
Inhaltszusammenfassung zur Seite Nr. 12
CY7C1161V18, CY7C1176V18 CY7C1163V18, CY7C1165V18 [3, 11] The write cycle descriptions of CY7C1165V18 follows. BWS BWS BWS BWS K K Comments 0 1 2 3 LLLL L–H – During the data portion of a write sequence, all four bytes (D ) are written into [35:0] the device. LLLL – L–H During the data portion of a write sequence, all four bytes (D ) are written into [35:0] the device. L H H H L–H – During the data portion of a write sequence, only the lower byte (D ) is written [8:0] into the device. D rem
Inhaltszusammenfassung zur Seite Nr. 13
CY7C1161V18, CY7C1176V18 CY7C1163V18, CY7C1165V18 Instruction Register IEEE 1149.1 Serial Boundary Scan (JTAG) Three-bit instructions are serially loaded into the instruction These SRAMs incorporate a serial boundary scan test access register. This register is loaded when it is placed between the TDI port (TAP) in the FBGA package. This part is fully compliant with and TDO pins as shown in “TAP Controller Block Diagram” on IEEE Standard 1149.1-2001. The TAP operates using JEDEC page 16. Upon pow
Inhaltszusammenfassung zur Seite Nr. 14
CY7C1161V18, CY7C1176V18 CY7C1163V18, CY7C1165V18 IDCODE PRELOAD enables an initial data pattern to be placed at the latched parallel outputs of the boundary scan register cells The IDCODE instruction causes a vendor-specific 32-bit code to before the selection of another boundary scan test operation. be loaded into the instruction register. It also places the instruction register between the TDI and TDO pins and enables The shifting of data for the SAMPLE and PRELOAD phases can the IDCODE to be
Inhaltszusammenfassung zur Seite Nr. 15
CY7C1161V18, CY7C1176V18 CY7C1163V18, CY7C1165V18 TAP Controller State Diagram [12] Figure 2. Tap Controller State Diagram TEST-LOGIC 1 RESET 0 1 1 1 TEST-LOGIC/ SELECT SELECT 0 IDLE DR-SCAN IR-SCAN 0 0 1 1 CAPTURE-DR CAPTURE-IR 0 0 SHIFT-DR 0 SHIFT-IR 0 1 1 1 1 EXIT1-DR EXIT1-IR 0 0 0 0 PAUSE-DR PAUSE-IR 1 1 0 0 EXIT2-DR EXIT2-IR 1 1 UPDATE-DR UPDATE-IR 1 1 0 0 Note 12. The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document Number: 001-06582 Rev. *D Page 15 o
Inhaltszusammenfassung zur Seite Nr. 16
CY7C1161V18, CY7C1176V18 CY7C1163V18, CY7C1165V18 TAP Controller Block Diagram Figure 3. Tap Controller Block Diagram 0 Bypass Register Selection Selection TDI 2 1 0 TDO Circuitry Circuitry Instruction Register 29 31 30 . . 2 1 0 Identification Register 106 . . . . 2 1 0 Boundary Scan Register TCK TAP Controller TMS TAP Electrical Characteristics [13, 14, 15] The Tap Electrical Characteristics table over the operating range follows. Parameter Description Test Conditions Min Max Unit V Output HIG
Inhaltszusammenfassung zur Seite Nr. 17
CY7C1161V18, CY7C1176V18 CY7C1163V18, CY7C1165V18 TAP AC Switching Characteristics [16, 17] The Tap AC Switching Characteristics over the operating range follows. Parameter Description Min Max Unit t TCK Clock Cycle Time 50 ns TCYC t TCK Clock Frequency 20 MHz TF t TCK Clock HIGH 20 ns TH t TCK Clock LOW 20 ns TL Setup Times t TMS Setup to TCK Clock Rise 5 ns TMSS t TDI Setup to TCK Clock Rise 5 ns TDIS t Capture Setup to TCK Rise 5 ns CS Hold Times t TMS Hold after TCK Clock Rise 5 ns TMSH t TD
Inhaltszusammenfassung zur Seite Nr. 18
CY7C1161V18, CY7C1176V18 CY7C1163V18, CY7C1165V18 Identification Register Definitions Value Instruction Field Description CY7C1161V18 CY7C1176V18 CY7C1163V18 CY7C1165V18 Revision Number 000 000 000 000 Version number. (31:29) Cypress Device ID 11010010001000101 11010010001001101 11010010001010101 11010010001100101 Defines the type of (28:12) SRAM. Cypress JEDEC ID 00000110100 00000110100 00000110100 00000110100 Enables unique (11:1) identification of SRAM vendor. ID Register 1 1 1 1 Indicate
Inhaltszusammenfassung zur Seite Nr. 19
CY7C1161V18, CY7C1176V18 CY7C1163V18, CY7C1165V18 Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID 0 6R 27 11H 54 7B 81 3G 1 6P 28 10G 55 6B 82 2G 26N 29 9G 56 6A 83 1J 3 7P 30 11F 57 5B 84 2J 4 7N 31 11G 58 5A 85 3K 57R 32 9F 59 4A 86 3J 6 8R 33 10F 60 5C 87 2K 7 8P 34 11E 61 4B 88 1K 8 9R 35 10E 62 3A 89 2L 9 11P 36 10D 63 1H 90 3L 10 10P 37 9E 64 1A 91 1M 11 10N 38 10C 65 2B 92 1L 12 9P 39 11D 66 3B 93 3N 13 10M 40 9C 67 1C 94 3M 14 11N 419D 68 1B 951N 15 9M 42 11B
Inhaltszusammenfassung zur Seite Nr. 20
CY7C1161V18, CY7C1176V18 CY7C1163V18, CY7C1165V18 Power Up Sequence in QDR-II+ SRA DLL Constraints During power up, when the DOFF is tied HIGH, the DLL gets ■ DLL uses K clock as its synchronizing input. The input must locked after 2048 cycles of stable clock. QDR-II+ SRAMs must have low phase jitter, which is specified as t KC Var be powered up and initialized in a predefined manner to prevent ■ The DLL functions at frequencies down to 120 MHz undefined operations. ■ If the input clock is unst
