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AT91SAM7L-STK Rev. A Starter Kit
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User Guide
6409A–ATARM–30-Jun-08
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1-2 AT91SAM7L-STK Rev. A Starter Kit User Guide 6409A–ATARM–30-Jun-08
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Table of Contents Section 1 Overview ....................................................................................................................1-1 1.1 Scope................................................................................................................................. 1-1 1.2 Deliverables ...................................................................................................................... 1-1 1.3 The AT91SAM7L-STK Rev. A Starter Board..................
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Table of Contents (Continued) 6.1 Q1 Footprint Incorrect........................................................................................................ 6-1 6.2 MAX3318 Control Pull-ups................................................................................................. 6-2 Section 7 Revision History .........................................................................................................7-1 ii AT91SAM7L-STK Rev. A Starter Kit User Guide 6409A–ATARM–30-Jun-08
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Section 1 Overview 1.1 Scope The AT91SAM7L-STK rev.A starter kit enables evaluation capabilities and code development of applica- tions running on an AT91SAM7L64/128. This guide focuses on the AT91SAM7L-STK rev.A board as an evaluation platform. 1.2 Deliverables The AT91SAM7L-STK rev.A package contains the following items: An AT91SAM7L-STK rev.A board Two AAA batteries 1.3 The AT91SAM7L-STK Rev. A Starter Board The board is equipped with an AT91SAM7L128 (128-lead LQFP package) together with t
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Section 2 Setting Up the AT91SAM7L-STK Rev. A Board 2.1 Electrostatic Warning The AT91SAM7L-STK rev.A starter board is shipped in a protective anti-static package. The board must not be subjected to high electrostatic potentials. A grounding strap or similar protective device should be worn when handling the board. Avoid touching the component pins or any other metallic element. 2.2 Requirements In order to set up the AT91SAM7L-STK rev.A starter board, the following items are needed: The AT91SA
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Setting Up the AT91SAM7L-STK Rev. A Board 2.3 Layout Figure 2-1. AT91SAM7L-STK Rev. A Board Layout 2.4 Powering Up the Board The AT91SAM7L-STK rev.A requires 3.0V (2.2V-3.6V) DC input. The power is supplied to the board via 2 AAA batteries or 3.0V VCC pads. 2.5 Getting Started Please refer to the AT91SAM product pages on the Atmel web site, for the most up-to-date information on getting started with the AT91SAM7L-STK rev.A. 2-2 AT91SAM7L-STK Rev. A Starter Kit User Guide 6409A–ATARM–30-Jun-08
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Setting Up the AT91SAM7L-STK Rev. A Board 2.6 AT91SAM7L-STK Rev. A Block Diagram Figure 2-2. AT91SAM7L-STK Block Diagram Interfaces SHEET 2 PC[0..29] PC[0..29] Interfaces Processor SHEET 4 AD[0..3] AD[0..3] PA[0..25] PA[0..25] PB[0..23] PB[0..23] PC[0..29] PC[0..29] ERASE Processor LCD, KBD SHEET 3 AD[0..3] AD[0..3] PA[0..25] PA[0..25] PB[0..23] PB[0..23] PC[0..29] PC[0..29] ERASE LCD, KBD AT91SAM7L-STK Rev. A Starter Kit User Guide 2-3 6409A–ATARM–30-Jun-08
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Section 3 Board Description 3.1 AT91SAM7L64/128 Microcontroller ® ® ® Incorporates the ARM7TDMI ARM Thumb Processor – High-performance 32-bit RISC Architecture – High-density 16-bit Instruction Set – Leader in MIPS/Watt ™ – EmbeddedICE In-circuit Emulation, Debug Communication Channel Support Internal High-speed Flash – 128 Kbytes (AT91SAM7L128), Organized in 512 Pages of 256 Bytes Single Plane – 64 Kbytes (AT91SAM7L64), Organized In 256 Pages of 256 Bytes Single Plane – Single Cycle Acces
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Board Description Debug Unit (DBGU) – Two-wire UART and Support for Debug Communication Channel interrupt, Programmable ICE Access Prevention Periodic Interval Timer (PIT) – 20-bit Programmable Counter plus 12-bit Interval Counter Windowed Watchdog (WDT) – 12-bit Key-protected Programmable Counter – Provides Reset or Interrupt Signals to the System – Counter may be Stopped While the Processor is in Debug State or in Idle Mode Real-time Clock (RTC) – Two Hundred Year Calendar with Alarm
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Board Description 3.2 AT91SAM7L64/128 Block Diagram Figure 3-1. AT91SAM7L64/128 Block Diagram CAPP1 TDI CAPM1 TDO Charge ICE CAPP2 ARM7TDMI JTAG TMS CAPM2 Pump SCAN TCK Processor VDDINLCD JTAGSEL VDD3V6 LCD VDDLCD System Controller Voltage Regulator VDDIO2 TST 2 MHz RCOSC FIQ 1.8 V VDDIO1 AIC IRQ0-IRQ1 Voltage GND Regulator VDDOUT PCK0-PCK2 VDDCORE CLKIN VDDIO2 Memory Controller SRAM PLLRC PLL PMC Embedded Address 2 Kbytes( Back-up) Flash XIN Decoder 4 Kbytes (Core) OSC Controller XOUT Abort Mi
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Board Description 3.3 Memory 6 Kbytes of Internal single-cycle access High-speed SRAM 64/128 Kbytes of Internal single-cycle access High-speed Flash 3.4 Clock Circuitry 32.768 KHz standard crystal for the oscillator 3.5 Reset Circuitry Internal reset controller with a bi-directional reset pin External reset push button 3.6 Shut Down controller Programmable shutdown and Wake-Up Wake-up push button. 3.7 Power Supply Circuitry For dynamic power consumption, the AT91SAM7L64/128 consumes a ma
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Board Description 3.11 PIO Usage Table 3-1. PIO Controller A I/O Line Peripheral A Peripheral B Peripheral Usage Powered by PA0 Segment LCD PANEL COM0 VDDIO2 PA1 Segment LCD PANEL COM1 VDDIO2 PA2 Segment LCD PANEL COM2 VDDIO2 PA3 Segment LCD PANEL COM3 VDDIO2 PA4 Segment LCD PANEL COM4 VDDIO2 PA5 Segment LCD PANEL COM5 VDDIO2 PA6 Segment LCD PANEL SEG0 VDDIO2 PA7 Segment LCD PANEL SEG1 VDDIO2 PA8 Segment LCD PANEL SEG2 VDDIO2 PA9 Segment LCD PANEL SEG3 VDDIO2 PA10 Segment LCD PANEL SEG4 VDDIO
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Board Description Table 3-2. PIO Controller B I/O Line Peripheral A Peripheral B Peripheral Usage Powered by PB0 Segment LCD PANEL SEG20 VDDIO2 PB1 Segment LCD PANEL SEG21 VDDIO2 PB2 Segment LCD PANEL SEG22 VDDIO2 PB3 Segment LCD PANEL SEG23 VDDIO2 PB4 Segment LCD PANEL SEG24 VDDIO2 PB5 Segment LCD PANEL SEG25 VDDIO2 PB6 Segment LCD PANEL SEG26 VDDIO2 PB7 Segment LCD PANEL SEG27 VDDIO2 PB8 Segment LCD PANEL SEG28 VDDIO2 PB9 Segment LCD PANEL SEG29 VDDIO2 PB10 Segment LCD PANEL SEG30 VDDIO2 PB
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Board Description Table 3-3. PIO Controller C I/O Line Peripheral A Peripheral B Peripheral Usage Powered by PC0 CTS1 PWM2 User’s Input Buttons OK VDDIO1 PC1 DCD1 TIOA2 User’s Input Buttons UP VDDIO1 PC2 DTR1 TIOB2 User’s Input Buttons RIGHT VDDIO1 PC3 DSR1 TCLK1 User’s Input Buttons DOWN VDDIO1 PC4 RI1 TCLK2 User’s Input Buttons LEFT VDDIO1 PC5 IRQ1 NPCS2 ZIGBEE IRQ1 VDDIO1 PC6 NPCS1 PCK2 ZIGBEE NPCS1 VDDIO1 PC7 PWM0 TIOA0 MAX3318E FORCEOFF VDDIO1 PC8 PWM1 TIOB0 ZIGBEE RSIN VDDIO1 PC9 PWM2 SCK
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Section 4 Configuration 4.1 Configuration Straps Table 4-1 gives details of configuration straps on the AT91SAM7L-STK rev. A starter board and their default settings. Table 4-1. Designation Default Setting Feature (1) J6 pins 39-40 Opened Closed for internal flash erase (2) J8 Closed VCC jumper SD1 Opened Disables VDDIO2 to VDDLCD connection SD2 2-3 Selects VCC or VDD3V6 to VDDLCD SD3 Closed Enables VDDOUT applying to VDDCORE SD4 2-3 Selects VDDINLCD input R20 IN Enables the ICE NRST input TP1
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Section 5 Schematics This section contains the following schematics: Top Level Interfaces LCD, KBD Processor AT91SAM7L-STK Rev. A Starter Kit User Guide 5-1 6409A–ATARM–30-Jun-08
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5 4 3 2 1 Interfaces SHEET 2 D D PC[0..29] PC[0..29] C C Interfaces SHEET 4 Processor AD[0..3] AD[0..3] PA[0..25] PA[0..25] PB[0..23] PB[0..23] PC[0..29] PC[0..29] ERASE Processor LCD, KBD SHEET 3 B B AD[0..3] AD[0..3] PA[0..25] PA[0..25] PB[0..23] PB[0..23] PC[0..29] PC[0..29] ERASE LCD, KBD A A A A A IIIN N NIIIT T T E E ED D DIIIT T T P P PP P P 1 1 17 7 7M M MA A AR R R0 0 08 8 8 X X XX X XX X X X X XX X X- - -X X XX X XX X X- - -X X XX X X R R RE E EV V V M M MO O OD D DIIIF F F... D
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5 4 3 2 1 J J1 1 PC[0..29] J J2 2 PC0 PC1 1 AAAAAA 1 PC2 PC3 P Pa ad d PC4 PC5 GND AAAAAA PC6 J J3 3 PC7 D D PC8 1 1 PC9 PC10 P Pa ad d PC11 PC12 VCC PC13 PC14 PC15 PC16 PC17 PC18 VCC U U1 1 VCC PC19 PC20 PC21 PC22 19 2 VCC C1+ C C2 2 PC23 C C1 1 1 10 00 0N NF F PC24 1 10 00 0N NF F R R1 1 R R3 3 PC25 18 4 R R2 2 GND C1- PC26 5 1 10 00 0K K 1 10 00 0K K 1 10 00 0K K SERIAL DEBUG PORT C2+ C C3 3 PC27 GND 1 10 00 0N NF F PC28 PC29 3 6 V+ C2- PC13 PC7 11 INVALID 7 V- C C4 4 C C5 5 PC14 PC12 1 READY
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5 4 3 2 1 B BP P1 1 PC1 UP PC[0..29] PB[0..23] 3 3- -1 14 43 37 75 56 65 5- -0 0 PC0 OK PA[0..25] B BP P2 2 B BP P3 3 B BP P4 4 PC2 RIGHT D D 3 3- -1 14 43 37 75 56 65 5- -0 0 3 3- -1 14 43 37 75 56 65 5- -0 0 3 3- -1 14 43 37 75 56 65 5- -0 0 PC4 LEFT B BP P5 5 PA0 COM0 PB0 SEG20 PC0 OK PC3 DOWN PA1 COM1 PB1 SEG21 PC1 UP PA2 COM2 PB2 SEG22 PC2 RIGHT PA3 COM3 PB3 SEG23 PC3 DOWN 3 3- -1 14 43 37 75 56 65 5- -0 0 PA4 COM4 PB4 SEG24 PC4 LEFT PA5 COM5 PB5 SEG25 PC5 PA6 SEG0 PB6 SEG26 PC6 PA7 SEG1 PB
