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PowerPC G5
The World’s First 64-Bit Desktop Processor
White Paper
July 2003
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White Paper 2 PowerPC G5 Contents Page 3 Introduction Page 4 The World’s First 64-Bit Desktop Processor An Exponential Leap in Computing Power Memory Addressing up to 18 Exabytes High-Precision Calculations in a Single Clock Cycle Clock Speeds up to 2GHz Industry-Leading 1GHz Frontside Bus Full Support for Symmetric Multiprocessing Native Compatibility with 32-Bit Application Code Page 7 Next-Generation PowerPC Architecture Ultrafast Access to Data and Instructions Highly Parallel Execution Cor
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White Paper 3 PowerPC G5 Introduction The revolutionary PowerPC G5 changes everything you know about personal computing. Key Features Suddenly, the next generation of high-performance applications for design and graphics, •64-bit architecture, capable of addressing media production, and scientific research is possible and practical on the desktop. That’s 18 exabytes of memory because the PowerPC G5 brings a 64-bit architecture to the Mac platform—ushering in •Clock speeds up to 2GHz an excitin
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White Paper 4 PowerPC G5 The World’s First 64-Bit Desktop Processor The PowerPC G5 marks the arrival of 64-bit performance to the personal computer market. With 64-bit-wide data paths and registers, this groundbreaking new processor can address vast amounts of main memory and handle multiple large integer and floating-point math calculations in a single clock cycle. 32-bit processing Postcard = 2 2 24 in. (155 cm ) An Exponential Leap in Computing Power The label “32-bit” or “64-bit” character
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White Paper 5 PowerPC G5 High-Precision Calculations in a Single Clock Cycle With 64-bit-wide data paths and registers, the PowerPC G5 can execute instructions on 64 bits of data in a single clock cycle—making it possible to perform huge integer calculations and highly precise floating-point mathematics. In contrast, a 32-bit pro- cessor would have to split up any data larger than 32 bits and process it over multiple clock cycles. The advanced calculation capability of the PowerPC G5 is critica
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White Paper 6 PowerPC G5 Native Compatibility with 32-Bit Application Code On other platforms, switching to a 64-bit computer requires migrating to a 64-bit operating system (and purchasing 64-bit applications) or running a 32-bit operating system in a slow emulation mode. With the PowerPC G5, the transition to a 64-bit system is seamless: Current 32-bit code—such as existing Mac OS X and Classic applications—runs natively at processor speed, with no interruptions to your work- flow and no a
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White Paper 7 PowerPC G5 Next-Generation PowerPC Architecture The PowerPC G5 is a highly parallel implementation of the PowerPC architecture, capable of handling multiple assorted tasks at the same time. It’s based on the execu- tion core of IBM’s 64-bit POWER4 processor—recipient of the Microprocessor Report’s 2001 Analyst’s Choice Award for Best Workstation/Server Processor, which recognizes excellence in semiconductor technology innovation, design, and implementation. With two double-precisi
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White Paper 8 PowerPC G5 PowerPC G5 Architecture Highly Parallel Execution Core At the heart of the PowerPC G5 is an entirely new superscalar, superpipelined execution core, composed of 12 functional units that execute different types of instructions con- currently for massive data throughput. Before instructions are dispatched into the Up to 215 in-flight instructions functional units, they are arranged into groups of up to five. Within the core alone, A wide architecture with 12 discrete proc
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White Paper 9 PowerPC G5 Optimized 128-Bit Velocity Engine The PowerPC G5 uses a dual-pipelined Velocity Engine optimized with two independent queues and dedicated 128-bit registers and data paths for efficient instruction and data flow. This 128-bit vector processing unit accelerates data manipulation by applying a sin- gle instruction to multiple data at the same time, known as SIMD processing. Originally implemented in the PowerPC G4, the Velocity Engine in the PowerPC G5 uses the same set o
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White Paper 10 PowerPC G5 Condition Register This special 32-bit register summarizes the states of the floating-point and integer units. The condition register also indicates the results of comparison operations and provides a means for testing them as branch conditions. By bridging information between the branch unit and other functional units, the condition register improves the flow of data throughout the execution core. Three-Component Branch Prediction Logic Advanced processors use branch
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White Paper 11 PowerPC G5 Industry-Leading Performance Ultrafast clock speeds and a highly parallel 64-bit architecture make the PowerPC G5 ideal for next-generation multimedia, graphics, and scientific applications. Integer and floating-point math calculations are faster than ever thanks to 64-bit-wide registers and data paths. To demonstrate the performance advantages of this groundbreaking new processor, Apple put the dual 2GHz Power Mac G5 to the test against the top-of-the-line Pentium 4–
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White Paper 12 PowerPC G5 SPECint_base2000 and SPECfp_base2000 measure the speed of a single task—either an integer calculation or a floating-point calculation—executing on a single processor. Each test measures how long the processor takes to complete the benchmark set of single tasks relative to a SPEC-defined baseline score. SPECint_base2000 is composed of eleven C and one C++ benchmark applications, including a chess program, a data compression utility, and a place-and-route simulator. SPECf
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White Paper 13 PowerPC G5 For comparisons that more accurately demonstrate the performance of a dual proces- sor system, VeriTest used the “SPEC rate” metrics, which recognize multiple processors. With SPECint_rate_base2000 and SPECfp_rate_base2000, the benchmark code is compiled and multiple copies are run concurrently, allowing both processors to work in parallel. SPEC rate tests determine the number of times a system can complete the benchmark per hour, also referred to as system throughput.
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White Paper 14 PowerPC G5 Technical Specifications 64-bit PowerPC processor architecture •Virtual address range: 64 bits, or 18 exabytes •Physical address range: 42 bits, or 4 terabytes •Full 64-bit data paths and registers •Native support for 32-bit application code •64K L1 instruction cache; 32K L1 data cache • 512K internal L2 cache •Dedicated data flow for dividing one instruction into two internal operations •Microcoded instructions for up to four internal operations • Support for up to e
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White Paper 15 PowerPC G5 Three-component branch prediction logic •Speculative superscalar inner core organization •Fast, selective flush of incorrect speculative instructions and results •Prediction of up to two branches per cycle • Support for up to 16 predicted branches in flight •Prediction hints added to branch instructions •Prediction support for branch direction and branch addresses Physical specifications •58 million transistors •130-nanometer, silicon-on-insulator (SOI) process •Die siz
