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CY14B101K
1 Mbit (128K x 8) nvSRAM With Real Time Clock
■ High reliability
Features
❐ Endurance to 200K cycles
■ 25 ns, 35 ns, and 45 ns access times
❐ Data retention: 20 years at 55°C
■ Pin compatible with STK17TA8 ■ Single 3V operation with tolerance of +20%, –10%
■ Data integrity of Cypress nvSRAM combined with full featured
■ Commercial and industrial temperature
Real Time Clock (RTC)
■ 48-Pin SSOP package (ROHS compliant)
❐ Low power, 350 nA RTC current
❐ Capacitor or battery backup for RT
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CY14B101K Pin Configurations Figure 1. 48-Pin SSOP 1 48 V V CC CAP A 2 47 A 16 15 A 46 14 3 HSB A 4 45 12 WE A 7 44 5 A 13 A 43 A 6 6 8 A 7 42 A 5 9 INT 8 41 NC A 4 9 40 A 11 39 10 NC NC 48-SSOP 11 38 NC NC 12 37 NC NC Top View 13 36 V V SS SS (Not To Scale) 35 NC 14 NC V 15 34 V RTCbat RTCcap DQ0 DQ 16 33 6 A 32 3 17 OE A 18 31 A 2 10 A 1 19 30 CE A 29 0 20 DQ7 DQ1 21 28 DQ5 DQ2 22 27 DQ4 x 1 26 DQ3 23 x 2 24 25 V CC Table 1. Pin Definitions Pin Name Alt IO Type Description A – A Input Addres
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CY14B101K pin from V . A STORE automatically disconnects the V Device Operation CAP CC operation is initiated with power provided by the V capacitor. CAP The CY14B101K nvSRAM consists of two functional compo- nents paired in the same physical cell. The components are Figure 2. AutoStore Mode SRAM memory cell and a nonvolatile QuantumTrap cell. The SRAM memory cell operates as a standard fast static RAM. Data V in the SRAM is transferred to the nonvolatile cell (the STORE CC operation), or from
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CY14B101K SRAM READ and WRITE operations that are in progress when The software sequence is clocked with CE controlled READs or HSB is driven LOW by any means are given time to complete OE controlled READs. After the sixth address in the sequence is before the STORE operation is initiated. After HSB goes LOW, entered, the STORE cycle commences and the chip is disabled. the CY14B101K continues SRAM operations for t . During It is important to use read cycles and not write cycles in the DELAY t ,
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CY14B101K Low Average Active Power Best Practices CMOS technology provides the CY14B101K the benefit of nvSRAM products have been used effectively for over 15 years. drawing significantly less current when it is cycled at times longer While ease-of-use is one of the product’s main system values, than 50 ns. Figure 3 shows the relationship between I and experience gained working with hundreds of applications has CC READ/WRITE Cycle Time. The worst case current consumption resulted in the followin
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CY14B101K Table 2. Mode Selection A15 – A0 Mode IO Power CE WE OE H X X X Not Selected Output High Z Standby L H L X READ SRAM Output Data Active L L X X WRITE SRAM Input Data Active [1, 2, 3] L H L 0x4E38 Read SRAM Output Data Active I CC2 Read SRAM Output Data 0xB1C7 0x83E0 Read SRAM Output Data 0x7C1F Read SRAM Output Data 0x703F Read SRAM Output Data 0x8FC0 Nonvolatile Output High Z STORE [1, 2, 3] L H L 0x4E38 Read SRAM Output Data Active 0xB1C7 Read SRAM Output Data Output Data 0x83E0 Rea
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CY14B101K The clock oscillator uses very little current to maximize the Real Time Clock Operation backup time available from the backup source. Regardless of clock operation with the primary source removed, the data stored nvTIME Operation in nvSRAM is secure, as it is stored in the nonvolatile elements The CY14B101K offers internal registers that contain clock, when power was lost. alarm, watchdog, interrupt, and control functions. RTC registers During backup operation, the CY14B101K consumes
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CY14B101K the match process. Depending on the match bits, the alarm Calibrating the Clock occurs as specifically as once a month or as frequently as once The RTC is driven by a quartz controlled oscillator with a nominal every minute. Selecting none of the match bits (all 1s) indicates frequency of 32.768 kHz. Clock accuracy depends on the quality that no match is required and therefore, alarm is disabled. of the crystal and calibration. The crystal oscillators typically Selecting all match bits
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CY14B101K the output pin driver on INT pin. These two bits are located in the Figure 4. Watchdog Timer Block Diagram Interrupt register and can be used to drive level or pulse mode output from the INT pin. In pulse mode, the pulse width is internally fixed at approximately 200 ms. This mode is intended Clock Oscillator 1 Hz Divider to reset a host microcontroller. In the level mode, the pin goes to its active polarity until the Flags register is read by the user. This 32,768 KHz 32 Hz mode is u
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CY14B101K Figure 5. Interrupt Block Diagram WDF Watchdog Timer WIE WDF - Watchdog Timer Flag WIE - Watchdog Interrupt V P/L CC Enable PF PF - Power Fail Flag Power Pin PFE - Power Fail Enable Monitor INT PFE Driver AF - Alarm Flag VINT AIE - Alarm Interrupt Enable H/L V SS P/L - Pulse Level H/L - High/Low AF Clock Alarm AIE Figure 6. RTC Recommended Component Configuration Recommended Values Y1 = 32.768KHz RF = 10M Ohm DQ 0 C1 = 0 (install cap footprint, but leave unloaded) A 3 C2 = 56 pF + 1
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CY14B101K [5, 6] Table 4. RTC Register Map [5] BCD Format Data Register Function/Range D7 D6 D5 D4 D3 D2 D1 D0 0x1FFFF 10s Years Years Years: 00–99 0x1FFFE 0 0 0 10s Months Months Months: 01–12 0x1FFFD 0 0 10s Day of Month Day Of Month Day of Month: 01–31 0x1FFFC 0 0 0 0 0 Day of Week Day of Week: 01–07 0x1FFFB 0 0 10s Hours Hours Hours: 00–23 0x1FFFA 0 10s Minutes Minutes Minutes: 00–59 0x1FFF9 0 10s Seconds Seconds Seconds: 00–59 [7] 0x1FFF8 OSCEN 0 Cal Sign Calibration (00000) Calibration V
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CY14B101K Table 5. Register Map Detail Time Keeping - Years D7 D6 D5 D4 D3 D2 D1 D0 0x1FFFF 10s Years Years Contains the lower two BCD digits of the year. Lower nibble (four bits) contains the value for years; upper nibble (four bits) contains the value for 10s of years. Each nibble operates from 0 to 9. The range for the register is 0–99. Time Keeping - Months D7 D6 D5 D4 D3 D2 D1 D0 0x1FFFE 0 0 0 10s Month Months Contains the BCD digits of the month. Lower nibble (four bits) contains the low
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CY14B101K Table 5. Register Map Detail (continued) Calibration/Control D7 D6 D5 D4 D3 D2 D1 D0 0X1FFF8 OSCEN 0 Calibration Calibration Sign OSCEN Oscillator Enable. When set to 1, the oscillator is stopped. When set to 0, the oscillator runs. Disabling the oscillator saves battery or capacitor power during storage. Calibration Determines if the calibration adjustment is applied as an addition (1) to or as a subtraction (0) from the time-base. Sign Calibration These five bits control the calib
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CY14B101K Table 5. Register Map Detail (continued) Alarm - Hours D7 D6 D5 D4 D3 D2 D1 D0 0x1FFF4 M 10s Alarm Hours Alarm Hours Contains the alarm value for the hours and the mask bit to select or deselect the hours value. M Match. When this bit is set to 0, the hours value is used in the alarm match. Setting this bit to 1 causes the match circuit to ignore the hours value. Alarm - Minutes D7 D6 D5 D4 D3 D2 D1 D0 0x1FFF3 M 10s Alarm Minutes Alarm Minutes Contains the alarm value for the minutes
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CY14B101K Package Power Dissipation Maximum Ratings Capability (T = 25°C) ................................................... 1.0W A Exceeding maximum ratings may impair the useful life of the Surface Mount Pb Soldering device. These user guidelines are not tested. Temperature (3 Seconds).......................................... +260°C Storage Temperature ................................. –65°C to +150°C DC Output Current (1 output at a time, 1s duration) ... 15 mA Ambient Temperature with Sta
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CY14B101K Data Retention and Endurance Parameter Description Min Unit DATA Data Retention 20 Years R NV Nonvolatile STORE Operations 200 K C Capacitance These parameters are guaranteed but not tested. Parameter Description Test Conditions Max Unit C Input Capacitance T = 25°C, f = 1 MHz, 7pF IN A V = 0 to 3.0 V CC C Output Capacitance 7 pF OUT Thermal Resistance These parameters are guaranteed but not tested. Parameter Description Test Conditions 48-SSOP Unit Θ Thermal Resistance Test conditi
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CY14B101K AC Switching Characteristics Parameter 25 ns 35 ns 45 ns Description Unit Cypress Alt. Min Max Min Max Min Max Parameter Parameter SRAM Read Cycle t t Chip Enable Access Time 25 35 45 ns ACE ELQV [11] t t t Read Cycle Time 25 35 45 ns RC AVAV, ELEH [12] t t Address Access Time 25 35 45 ns AA AVQV t t Output Enable to Data Valid 12 15 20 ns DOE GLQV [12] t t Output Hold After Address Change 3 3 3 ns OHA AXQX [13] t t Chip Enable to Output Active 3 3 3 ns LZCE ELQX [13] t t Chip Disable
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CY14B101K AC Switching Characteristics (continued) Parameter 25 ns 35 ns 45 ns Description Unit Cypress Alt. Min Max Min Max Min Max Parameter Parameter SRAM Write Cycle t t Write Cycle Time 25 35 45 ns WC AVAV t t t Write Pulse Width 20 25 30 ns PWE WLWH, WLEH t t t Chip Enable To End of Write 20 25 30 ns SCE ELWH, ELEH t t t Data Setup to End of Write 10 12 15 ns SD DVWH, DVEH t t t Data Hold After End of Write 0 0 0 ns HD WHDX, EHDX t t t Address Setup to End of Write 20 25 30 ns AW AVWH, AVE
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CY14B101K AutoStore or Power Up RECALL CY14B101K Parameter Description Unit Min Max [18] t Power Up RECALL Duration 40 ms HRECALL [19, 20] t STORE Cycle Duration Commercial 12.5 ms STORE Industrial 15 ms V Low Voltage Trigger Level 2.65 V SWITCH t VCC Rise Time 150 μs VCCRISE Figure 12. AutoStore/Power Up RECALL STORE occurs only No STORE occurs without atleast one if a SRAM write has happened SRAM write V CC V SWITCH t VCCRISE AutoStore t t STORE STORE POWER-UP RECALL t t HRECALL HRECALL R
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CY14B101K [21, 22] Software Controlled STORE/RECALL Cycles 25 ns 35 ns 45 ns Alt. Parameter Description Unit Parameter Min Max Min Max Min Max t t STORE/RECALL Initiation Cycle 25 35 45 ns RC AVAV Time t t Address Setup Time 0 0 0 ns SA AVEL t t Clock Pulse Width 20 25 30 ns CW ELEH t t Address Hold Time 1 1 1 ns HA EHAX t RECALL Duration 170 170 170 μs RECALL [22] Figure 13. CE Controlled Software STORE/RECALL Cycle t t RC RC ADDRESS # 1 ADDRESS # 6 ADDRESS t t SA SCE CE t HA OE tSTORE / t
