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Application Report
SPRA921 - June 2003
TMS320C6713 Digital Signal Processor Optimized for High
Performance Multichannel Audio Systems
Roshan Gummattira, Philip Baltz, DSP Applications
Nat Seshan
ABSTRACT
The TMS320C6713’s high performance CPU and rich peripheral set are tailored for
multichannel audio applications such as broadcast and recording mixing, home and large
venue audio decoders, and multi-zone audio distribution. The TMS320C6713 device is
based on the high-performance advanced VelociT
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SPRA921 4 McASP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.1 McASP Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.2 TDM Synchronous Transfer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.3 DIT Transfer Mode . . . . . . . . .
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SPRA921 • Glueless external memory interface (EMIF) capable of interfacing to SDRAM for bulk external storage of additional code or delay buffers. The EMIF also supports synchronous burst SRAM (SBSRAM), asynchronous memories, and peripherals with parallel interfaces. • A host-port interface (HPI) for direct connection to a host processor Figure 3 shows additional peripherals and the internal connection of the device. This includes: • A highly efficient 16-channel enhanced direct memory access (E
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SPRA921 Directly connected to other system SDRAM components EMIF GPIO McASP McASP Multiple serial TMS320C6713 Multiple serial port 0 port 0 input streams digital output streams (A/D converters, signal (D/A converters, DIR/SPDIF McASP processor McASP DIT/SPDIF line receivers) port 1 port 1 converters) HPI IIC IIC Serially Host ROM controlled processor interface devices Figure 2. Generalized High Performance Multichannel Audio System C6713 digital signal processor 32 EMIF L1P cache L2Cache/ direct
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SPRA921 2 C67x CPU and Instruction Set The TMS320C6713 floating-point digital signal processor uses the C67x VelociTI advanced very-long instruction words (VLIW) CPU. The CPU fetches (256 bits wide) to supply up to eight 32-bit instructions to the eight functional units during every clock cycle. The VelociTI VLIW architecture also features variable-length execute packets; these variable-length execute packets are a key memory-saving feature, distinguishing the C67x CPU from other VLIW architectu
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SPRA921 Table 1. C6713 Benchmark Performance Algorithm Description Parameter Values Cycles Time Biquad filter nx input/output cycles nx = 60 316 1.4 µ s (IIR filter direct form II) nx = 90 436 1.9 µ s Real FIR filter nh coefficients nh = 24 802 3.6 µ s nr output samples nr = 64 nh = 30, nr = 50 795 3.5 µ s IIR filter nr number of output samples nr = 64 443 2.0 µ s IIR lattice filter nr number of samples nk = 10, 4125 18.3 µ s nk number of reflection coefficients nr = 100 Dotproduct nx number of
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SPRA921 3.3 Unified L2 for Program and Data By unifying the program and data in the L2 space, the L2 cache is more likely to hold the memory requested by the CPU. It enables the on-chip memory to contain more data than program when highly computational, looping code is being run to process large data streams. For long, serial code with few data accesses, the L2 may be more densely populated with program instructions. The unification allows you to allocate the appropriate amount of memory for bot
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SPRA921 3.5 Cache Summary The efficiency of the cache architecture makes the device simple to use. The cache is inherently transparent to the user. Due to the level of associativity and the high cache hit rate, virtually no optimization must be done to achieve high performance. Reduced time for optimization leads to reduced development time, allowing functional systems to be up and running quickly. High performance can be immediately achieved with the cache architecture, while a Harvard architec
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SPRA921 In the TDM synchronous transfer mode, the McASP continually transmits and receives data periodically (since audio ADCs and DACs operate at a fixed-data rate). The data is organized into frames. In a typical audio system, one frame is transferred per sample period. To support multiple channels, the choices are to either include more time slots per frame (and therefore operate with a higher bit clock) or to keep the bit clock period constant and use additional data pins to transfer the sam
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SPRA921 A typical usage for the frame sync pins is to carry the left-right clock (LRCLK) signal when transmitting and receiving stereo data. The frame sync signals are individually programmable for either internal or external generation, either bit or slot length, and either rising or falling edge polarity. Some examples of the things that a system designer can use the McASP clocking flexibility for are: • Input a high-frequency master clock (for example, 512fs of the receiver), receive with an
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SPRA921 6 References 1. TMS320C6713 Floating-Point Digital Signal Processor data sheet (SPRS186) 2. TMS320C6211Cache Analysis application report (SPRA472) 3. TMS320C6000 DSP Multichannel Audio Serial Port (McASP) Reference Guide (SPRU041) 4. TMS320C621x/C671x Two-Level Internal Memory Reference Guide (SPRU609) 5. TMS320C6000 CPU and Instruction Set Reference Guide (SPRU189) 6. TMS320C6000 Peripherals Reference Guide (SPRU190) 7. Payan, Reimi, DSP software and hardware trade-offs in Professional
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