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Philips Semiconductors Objective Specification, Revision 2.2 4 DESCRIPTION The +/- 5.0 volt pre-amplifier for HDD described here has been designed for 12 terminals, comprised of a SAL or GMR magneto-resistive reader and an inductive thin film writer. In read mode, the device operates as a low noise differential preamplifier which senses resistance changes in the MR element that correspond to flux changes on the disk. In write mode, the circuit operates as a thin film head current switch, dri
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Philips Semiconductors Objective Specification, Revision 2.2 6 BLOCK DIAGRAM R O T Av RDp X R C U On/Off R E E M V / I F M R TA handling Av out D + F RDn Rin:2bits R R A U O E B C H d/dt RFE A 4 bits 3bits 1.5 bit T Read Back End R FAULT M TA handling MR BIAS R Rin:2bits RFE Rmr measure SDATA temperatue SERIAL 5 bits SCLK DIGITIZER r t i e b v i 1 : r t d WRITE s - o e Rext r o BANDGAP CURRENT p b 5 bits Interface t i r b e v 1 i r t d s - o e r o p b 1998 July 30 6 driven voltage 1 bit b
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Philips Semiconductors Objective Specification, Revision 2.2 7 PAD ARRANGEMENT DRN WN7 BFAST 1 1 1 0 0 1 0 0 9 9 9 8 8 8 8 1 9 E 1 1 1 1 1 1 1 N P P N P N N P E P P N N P N N P R R V W W R R W W WP7 W R R R W R W W SDATA SCLK RP7 SEN RN7 FLT WDP RN6 WDN VCC VCC VCC RP6 RWN WP6 SHIELDN WN6 RDN GND GND RDP CS0 SHIELDP WN5 REXT WP5 CS1 RP5 VCC VCC RN5 RN4 RP4 N WP4 W 0 0 1 2 2 2 3 T 0 0 1 1 1 2 3 3 3 E N P P N N P P N N P P N N P P N S E R R R W R R W R R R V W W W W W W WN4 Fig.2 TDA5360 pad arr
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Philips Semiconductors Objective Specification, Revision 2.2 8 PAD DESCRIPTION SYMBOL Pin Description VCC +5V supply GND Ground VEE -5V supply RDP,RDN output Read Data, Differential read signal outputs RWN logic input Read/Write : read = HIGH, write = LOW WDP,WDN input Differential PECL or current mode write data input FLT output In Write mode, a fault is flagged when FLT is high. In Read Mode, a fault is flagged when FLT is low. a 5k Ω external resistor must be connected between FLT and VCC. in
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Philips Semiconductors Objective Specification, Revision 2.2 9 FUNCTIONAL DESCRIPTION 9.1 Active READ mode Taking RWN high and programming bits MODE0 and MODE1 (see Reg.09) selects the read mode. The Head select inputs, in serial register, select the appropriate head. In read mode, the circuit provides either a constant power bias or a constant current bias that flows from the P to the N side of the MR section of the head. The value of the current/power is programmed in Reg. 02 and is referen
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Philips Semiconductors Objective Specification, Revision 2.2 9.2 Active WRITE mode select the appropriate head. In write mode the circuit acts as a current switch with write current toggled between the P and N directions of the thin- film section of the selected head x. The signal polarity is noninverting from WDP, WDN to WPx, WNx. (set LOW or HIGH respectively.) The polarity convention for current mode is : “positive” => input pin with minimum current flowing “negative” => input pin with ma
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Philips Semiconductors Objective Specification, Revision 2.2 9.5 SLEEP mode The sleep mode is selected by programming bits MODE0 and MODE1. (see Reg.09) In Sleep Mode, the IC is accessible via the Serial Interface. All circuits, other than those of the CMOS Serial Interface and the circuit which forces the data registers to their default values at power up and which fixes the DC level of RDp- one mA, depending on the state of the logic pins where internal pull-up or pull-down resistors are conn
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Philips Semiconductors Objective Specification, Revision 2.2 10 BIASING OF THE MR ELEMENT This preamplifier has been designed for SAL and GMR elements. Programming bit GMR in Reg. 01 select either a SAL range (LOW) or a GMR range (HIGH). By programming bit PORI in Reg. 01, the user can program either a constant current bias (LOW) or a constant power bias (HIGH) for the MR element. The value of the current/power is programmed on 5 bits via Reg. 02. If bit PORI in Reg. 01 is HIGH, a constant pow
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Philips Semiconductors Objective Specification, Revision 2.2 10.2 Fault Mode Fault conditions are indicated on the FLT pin (HIGH during write mode and LOW during read mode). The fault condition writing to Reg.09 The FLT output is an open collector to an external resistor of 5Kohms connected to +5V. Table 1: Fault Conditions Mode Fault condition FCOD3 FCOD2 FCOD1 FCOD0 Both No fault 0 0 0 0 Read Write current present 0 0 0 1 Fault code not used 0 0 1 0 Thermal Asperity detected 0 0 1 1 Read head
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Philips Semiconductors Objective Specification, Revision 2.2 The following are valid READ fault conditions which set FLT=LOW • Rext pin open or shorted to GND or Vcc • Thermal Asperity detected • Read Head open • Power supplies too low (VCC and/or VEE) • Write current present in read mode • Illegal head address ( i.e. head 12, 13, 14 or 15) In this case, besides asserting the fault flag, the MR bias current is diverted to the dummy head. The following are valid WRITE fault conditions which set
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Philips Semiconductors Objective Specification, Revision 2.2 10.3 Serial Interface Address bit Allocation Register A 7 A 6 A 5 A 4 A 3 A 2 A 1 A 0 0 X 0 0 0 0 CS1 CS0 RWN 1 X 0 0 0 1 CS1 CS0 RWN 2 X 0 0 1 0 CS1 CS0 RWN 3 X 0 0 1 1 CS1 CS0 RWN 4 X 0 1 0 0 CS1 CS0 RWN 5 X 0 1 0 1 CS1 CS0 RWN 6 X 0 1 1 0 CS1 CS0 RWN 7 X 0 1 1 1 CS1 CS0 RWN 8 X 1 0 0 0 CS1 CS0 RWN 9 X 1 0 0 1 CS1 CS0 RWN 10 X 1 0 1 0 CS1 CS0 RWN 11 X 1 0 1 1 CS1 CS0 RWN 10.4 Serial Interface Register bit Allocation 9 Register D 7 D
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Philips Semiconductors Objective Specification, Revision 2.2 10.5 Serial Interface Operations The serial interface communication consists of an adress word of 8 bits followed by a data word of 8 bits. See section 11, page 24 and 25 for timing diagrams. 10.5.1 S E R I A L A D D R E S S I N G When SEN goes HIGH, bits are latched-in at rising edges of SCLK. The first eight bits a7-a0 starting with the LSB, are shifted serially into an address register. If SEN goes LOW before 16 bits have been fo
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Philips Semiconductors Objective Specification, Revision 2.2 10.6 Registers description Nb Register Name Contents 0 Head Select Register HS3..HS0 = 0,0,0,0 to 1,0,1,1 = H0 to H11 SELT : if HIGH, the multiple selection detector is enabled. Inactive in STW mode SELF : is set HIGH if illegal MDS is detected (read back only bit) ( Note 0 ) LCS1,LCS0 : copy of CS1,CS0 pins state (read back only bits) 1 Control Register PORI : Select a MR Bias mode. LOW = Current Bias HIGH = Power Bias GMR : select
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Philips Semiconductors Objective Specification, Revision 2.2 3 Reader Bandwith HFZ3, HFZ2, HFZ1, HFZ0 = high frequency gain boost/ differentiator control Register ( Note 3 ) LFP1, LFP0 = low frequency pole. (0,0) = 1 MHz (0,1) = 2 MHz (1,0) = 3 MHz (1,1) = 4 MHz 4 Writer Bias Register IW4, IW3, IW2, IW1, IW0 = 5 bits to define Iwr current : Iwr = 10mA + 1.3mA*(IW0+2*IW1+4*IW2+8*IW3+16*IW4) WCP2...WCP1 = 3 bits for the write current overshoot (Note 4) 5 Thermal Asperity TRANGE = if HIGH, the TA
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Philips Semiconductors Objective Specification, Revision 2.2 8 Measurement Register M4...M0 = 5 bits for Rmr/Temperature digitazation (read back only bits) RANGE1,RANGE0 = 2bits to define which measurement to be done (0,0) RMR measurement for 15 Ω < Rmr < 46 Ω Rmr = 698 / (15.5 + M0 + 2*M1 + 4*M2 + 8*M3 + 16*M4) (0,1) and (1,0) : RMR measurement for 40 Ω < Rmr < 90 Ω Rmr = 2094 / ( 21 + M0 + 2*M1 + 4*M2 + 8*M3 + 16*M4 ) (1,1) = Temperature measurement Temp = 473K - 4.6K * (M0 + 2*M1 + 4*M2 + 8*M
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Philips Semiconductors Objective Specification, Revision 2.2 Note 0 : MDS (Multiple Device Selected) detector : When several preamps are connected in parallel, this function allows the user detection of wrong adressing withing the preamps. When SELT is high, the selected preamp pull a precise current on FLT pin. If only one preamp has reacted, SELF is LOW. If more than one preamp has reacted, the voltage on FLT pin is lower than a reference voltage and thus SELF is HIGH. Note 1a : The Write pa
