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Intel® Server Board SDS2
Technical Product Specification
Order Number: A85874-002
Revision 1.2
December 2, 2002
Enterprise Platforms and Services Marketing
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Revision History Intel® Server Board SDS2 Revision History Date Revision Modifications Number 9/20/2001 1.0 Initial release. 5/15/2002 1.1 Added Section 13: Errata. Corrected miscellaneous document errors. Added Table 6.2.5.4: Baseboard Management Controller (BMC) Beep Code Generation. 12/2/02 1.2 Added Errata 19-37 that are corrected with FAB5. Updated Table 6.2.5.4. Added Table 25. ii Revision 1.2 Order Number: A85874-002
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Intel® Server Board SDS2 Disclaimers Disclaimers ® Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or w
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Table of Contents Intel® Server Board SDS2 Table of Contents 1. Introduction .............................................................................................................................1 2. Architecture.............................................................................................................................2 3. Processor and Chipset..........................................................................................................4 3.1 Processors ..
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Intel® Server Board SDS2 Table of Contents 4.6.2 BIOS Flash..................................................................................................................20 4.7 Interrupt Routing ...............................................................................................................20 4.7.1 Legacy Interrupt Routing.............................................................................................20 4.7.2 APIC Interrupt Routing .............................
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Table of Contents Intel® Server Board SDS2 6.3.4 Clearing CMOS...........................................................................................................67 6.4 Flash Update Utility...........................................................................................................67 6.4.1 Loading the System BIOS ..........................................................................................67 6.4.2 User Binary Area.............................................
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Intel® Server Board SDS2 Table of Contents 8.9 Connector Manufacturers and Part Numbers..................................................................87 9. Jumpers..................................................................................................................................88 9.1 System Configuration Jumpers........................................................................................88 9.2 Performing CMOS Clear, BIOS Recovery, and BMC Force Update............
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Table of Contents Intel® Server Board SDS2 5. Intel® & ICP Vortex* RAID Controllers will cause the Intel® Server Board SDS2 to halt during POST when the BIOS Logo screen is enabled.............................................................109 6. Intel® Server Board SDS2 CD-ROM issues..................................................................110 7. NIC driver set 5.12 v.2.3.15 for UnixWare* 7.1.1 drops DPC LAN connection..............111 8. NIC driver set 5.12 v.5.41.27 for Microsof
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Intel® Server Board SDS2 Table of Contents 34. Peer-to-peer PCI transactions are not supported between the CIOB-controlled 64-bit PCI bus and the legacy 32-bit PCI bus controlled by the HE-SL north bridge .........................125 35. SDS2 PCI slot current levels supported by the 5V rail...................................................125 36. OB P100 NICs do not show at POST but attempt PXE boot and appear in Boot Menu125 Glossary........................................................
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List of Figures Intel® Server Board SDS2 List of Figures Figure 1. SDS2 Server Board Block Diagram .................................................................................1 Figure 2. SDS2 Memory Bank Layout..............................................................................................7 Figure 3. SDS2 Interrupt Routing Diagram (CSB5 Internal)..........................................................22 Figure 4. SDS2 Interrupt Routing Diagram...........................
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Intel® Server Board SDS2 List of Tables List of Tables Table 1. SDS2 Intel® Pentium® III Processor Support Matrix.........................................................4 Table 2. Memory DIMM Pairs...........................................................................................................7 2 Table 3. I C Addresses for DIMM Slots............................................................................................8 Table 4. PCI Bus Segment Characteristics...............
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List of Tables Intel® Server Board SDS2 Table 32. Main Menu Selections ....................................................................................................55 Table 33. Primary Master and Slave IDE Submenu Selections ....................................................56 Table 34. Processor Settings Submenu Selections......................................................................57 Table 35. Advanced Menu Selections.......................................................
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Intel® Server Board SDS2 List of Tables Table 66. IDE 40-pin Connector Pin-out........................................................................................82 Table 67. Stacked Three-port USB Connector Pin-out .................................................................82 Table 68. 10-pin USB Connection Header (2 x 5) Pin-out.............................................................83 Table 69. 34-pin Floppy Connector Pin-out ................................................
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List of Tables Intel® Server Board SDS2 < This page intentionally left blank. > xi v Revision 1.2 Order Number: A85874-002
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Intel® Server Board SDS2 Introduction 1. Introduction This chapter provides an architectural overview of the Intel® SDS2 Server Board. It provides a view of the functional blocks and their electrical relationships. The figure below shows the functional blocks of the Server Board and the plug-in modules that it supports. CPU 1 CPU 2 Front Side Bus (133MHz) APIC Bus FLASH DATA Bus (133MHz) IDE Pri Registers ADD/CTRL Bus (133MHz) PCI 32-bit Bus (33MHz, 5V) Registers CSB5 HE-SL
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Architecture Intel® Server Board SDS2 2. Architecture ® ® The SDS2 Server Board is a monolithic printed circuit board that can accept two Intel Pentium III processors using the Socket 370 FCPGA2 package. The SDS2 Server Board complies with the Entry SSI version 1.0 and ATX version 2.03 (12 inch x 13 inch) form-factor. It is designed around the Server Works* ServerSet* III HE-SL chipset. The chipset contains three components: • The HE-SL CNB20 North Bridge provides an integrated memor
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Intel® Server Board SDS2 Architecture • 64-bit, 66-MHz 3.3 V full-length PCI segment C (P64-C) with one embedded device - Dual Channel Wide Ultra160 SCSI controller: Adaptec* AIC-7899W - Two 64-bit 3.3 V Slots: PCI slots 5 and 6 • LPC (Low Pin Count) bus segment with two embedded devices - Baseboard Management Controller (BMC) providing monitoring, alerting, and logging of critical system information obtained from embedded sensors on the Server Board - Super I/O controller chip providing
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Processor and Chipset Intel® Server Board SDS2 3. Processor and Chipset The Server Works* ServerSet III HE-SL chipset provides the 36-bit address, 72-bit data (64-bit data + 8-bit ECC) processor host bus interface, operating at 133 MHz in the AGTL signaling environment. The HE-SL North Bridge provides an integrated memory controller, the interface to 32-bit, 33-MHz Rev 2.2 compliant PCI bus, and two Inter-Module Bus interfaces. The Inter- Module Bus (IMB) provides the interface to two 64-
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Intel® Server Board SDS2 Processor and Chipset Pentium III – SL5XL Tray Intel FCPGA2 843849 1.4GHZ/133MHz 512KB tA1 06B1h Yes Pentium III – SL5XL Boxed Notes: • All processor sockets must be populated with either a processor or a terminator module. The BMC will not allow DC power to be applied to the system unless both processor sockets contain a properly seated processor or terminator module. • Processors should be populated in the sequential order. In other words, proce
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Processor and Chipset Intel® Server Board SDS2 3.1.1 Processor Voltage Regulator Module (VRM) The SDS2 Server Board has dual, on board, RM circuitry to support the two processors. The circuit is compliant with the VRM8.5 specification and provides a maximum of 60A, which will support the currently available processors and future releases of the Pentium III processors. The board hardware and the BMC read the processor VID (Voltage Identification) bits for each processor before turning on
