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MICROCOMPUTER MN1030
MN103001G/F01K
LSI User’s Manual
Pub.No.23101-050E
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PanaX Series is a trademark of Matsushita Electric Industrial Co., Ltd. The other corporation names, logotype and product names written in this book are trademarks or registered trademarks of their corresponding corporations. Request for your special attention and precautions in using the technical informaition and semiconductors described in this book (1) An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies descr
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Table of Contents/List of Figures and Tables 0 1. General Specifications 1 2. CPU 2 3. Extension Instruction Specifications 3 4. Memory Modes 4 5. Operating Mode 5 6. Clock Generator 6 7. Internal Memory 7 8. Bus Controller (BC) 8 9. Interrupt Controller 9 10. 8-bit Timers 10 11. 16-bit Timers 11 12. Watchdog Timer 12 13. Serial Interface 13
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14. A/D Converter 14 15. I/O Ports 15 16. Internal Flash Memory 16 17 17. Ordering Mask ROM Appendix
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Table of Contents/List of Figures and Tables 0
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Table of Contents 1. General Specifications 1.1 Overview ........................................................................................................................ 1-2 1.2 Features .......................................................................................................................... 1-2 1.3 Block Diagram ............................................................................................................... 1-4 1.4 Pin Description.........................
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5. Operating Mode 5.1 Overview ........................................................................................................................ 5-2 5.2 Reset Mode .................................................................................................................... 5-3 5.3 Low Power Mode ........................................................................................................... 5-4 6. Clock Generator 6.1 Overview .............................................
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8.13.2 16-bit Bus with Handshaking, in Synchronous Mode and in Address/Data Separate Mode ...................................................................... 8-35 8.13.3 16-bit Bus in Asynchronous Mode and in Address/Data Separate Mode ............................................................................................ 8-37 8.13.4 8-bit Bus with Fixed Wait States, in Synchronous Mode and in Address/Data Separate Mode ........................................................... 8-39 8.1
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10.6 Description of Operation............................................................................................ 10-20 10.6.1 Interval Timers and Timer Output ............................................................ 10-20 10.6.2 Event Counting ......................................................................................... 10-24 10.6.3 Cascaded Connection ................................................................................ 10-26 10.6.4 PWM Output ...............
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13.4.2 Block Diagram of UART Serial Interface ................................................ 13-37 13.4.3 Description of Registers for the UART Serial Interface ........................... 13-38 13.4.4 Description of Operation........................................................................... 13-45 14. A/D Converter 14.1 Overview ...................................................................................................................... 14-2 14.2 Features ....................
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15.9.3 Pin Configurations .................................................................................... 15-44 15.10 Port 8 .......................................................................................................................... 15-45 15.10.1 Block Diagram .......................................................................................... 15-45 15.10.2 Register Descriptions ................................................................................ 15-46 15.10
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List of Figures and Tables List of Figures 1. General Specifications Fig. 1-3-1 MN103001G Block Diagram .................................................................................... 1-4 Fig. 1-4-1 Pin Assignments Diagram ......................................................................................... 1-5 2. CPU Fig. 2-2-1 CPU Core Block Diagram ......................................................................................... 2-3 Fig. 2-3-1 CPU Registers ..................
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Fig. 8-7-1 Address Format When Accessing External Memory .............................................. 8-26 Fig. 8-7-2 Space Partitioning....................................................................................................8-27 Fig. 8-12-1 Internal I/O Space Access ....................................................................................... 8-31 Fig. 8-13-1 Access Timing on a 16-bit Bus with Fixed Wait States, in Synchronous Mode and in Address/Data Separate Mode (MCLK
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Fig. 8-13-21 Access Timing on a 16-bit Bus with Handshaking, in Synchronous Mode and in Address/Data Multiplex Mode (MCLK = SYSCLK multiplied by 2) ................ 8-49 Fig. 8-13-22 Access Timing on a 16-bit Bus with Handshaking, in Synchronous Mode and in Address/Data Multiplex Mode (MCLK = SYSCLK) ......................................... 8-50 Fig. 8-13-23 Access Timing on a 16-bit Bus in Asynchronous Mode and in Address/Data Multiplex Mode (MCLK = SYSCLK multiplied by 4) ................ 8-5
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10. 8-bit Timers Fig. 10-3-1 8-bit Timer Block Diagram (Timers 0 to 3) ............................................................ 10-3 Fig. 10-3-2 8-bit Timer Block Diagram (Timers 4 to B) ........................................................... 10-4 Fig. 10-3-3 8-bit Timer Connection Diagram (Overall)............................................................. 10-5 Fig. 10-3-4 8-bit Timer Connection Diagram (Timer 0 to 3 block) ........................................... 10-6 Fig. 10-3-5
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12. Watchdog Timer Fig. 12-3-1 Block Diagram ........................................................................................................ 12-3 Fig. 12-5-1 Operation Diagram 1: When Reset Is Released ...................................................... 12-7 Fig. 12-5-2 Operation Diagram 2: When Recovering from STOP Mode .................................. 12-8 Fig. 12-5-3 Operation Diagram 3: Watchdog Operation ........................................................... 12-9 13. Seri
