Inhaltszusammenfassung zur Seite Nr. 1
LogiCORE™ IP
Ethernet 1000BASE-X
PCS/PMA or SGMII v9.1
User Guide
UG155 March 24, 2008
R
Inhaltszusammenfassung zur Seite Nr. 2
R Xilinx is disclosing this Specification to you solely for use in the development of designs to operate on Xilinx FPGAs. Except as stated herein, none of the Specification may be copied, reproduced, distributed, republished, downloaded, displayed, posted, or transmitted in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Any unauthorized use of this Specification may violate cop
Inhaltszusammenfassung zur Seite Nr. 3
Table of Contents Schedule of Figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Schedule of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Preface: About This Guide Guide Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Conventions . . . . . . .
Inhaltszusammenfassung zur Seite Nr. 4
R Implement the Ethernet 1000BASE-X PCS/PMA or SGMII Core in Your Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Chapter 5: Using the Client-side GMII Data Path Designing with the Client-side GMII for the 1000BASE-X Standard. . . . . . . . . . . . 53 GMII Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 GMII Reception . . . . . . . . . . . . . .
Inhaltszusammenfassung zur Seite Nr. 5
R Virtex-5 LXT and SXT Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Virtex-5 FXT Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Chapter 9: Configuration and Status MDIO Management Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 MDIO Bus System . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Inhaltszusammenfassung zur Seite Nr. 6
R Virtex-5 RocketIO GTX Transceivers for SGMII or Dynamic Standards Switching Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 Ten-Bit Interface Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 Constraints When Implementing an External GMII . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 Understanding Timing Reports for Setup/Hold Timing . . . . . . . . . . . .
Inhaltszusammenfassung zur Seite Nr. 7
R Appendix B: Core Latency Core Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 Latency for 1000BASE-X PCS with TBI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 Latency for 1000BASE-X PCS and PMA Using a RocketIO Transceiver . . . . . . . . . . 208 Latency for SGMII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Inhaltszusammenfassung zur Seite Nr. 8
R www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008
Inhaltszusammenfassung zur Seite Nr. 9
Schedule of Figures Chapter 2: Core Architecture Figure 2-1: Functional Block Diagram Using RocketIO Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 2-2: Functional Block Diagram with a Ten-Bit Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 2-3: Component Pinout Using RocketIO Transceiver with PCS Management Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure
Inhaltszusammenfassung zur Seite Nr. 10
R Chapter 6: The Ten-Bit Interface Figure 6-1: Ten-Bit Interface Transmitter Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Figure 6-2: Ten-Bit-Interface Receiver Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Figure 6-3: TBI Receiver Logic for Spartan-3, Spartan-3E, and Spartan-3A Devices. . . . . . . . . . . . . 72 Figure 6-4: Ten-Bit Interface Receiver Logic - Virtex-4 Device (Exampl
Inhaltszusammenfassung zur Seite Nr. 11
R Chapter 11: Dynamic Switching of 1000BASE-X and SGMII Standards Figure 11-1: Typical Application for Dynamic Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Chapter 12: Constraining the Core Figure 12-1: Local Clock Place and Route for Top MGT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Figure 12-2: Input TBI timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Inhaltszusammenfassung zur Seite Nr. 12
R www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008
Inhaltszusammenfassung zur Seite Nr. 13
Schedule of Tables Chapter 2: Core Architecture Table 2-1: GMII Interface Signal Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 2-2: Other Common Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 2-3: Optional MDIO Interface Signal Pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 2-4: Optional Configuration and Status Vectors . . . . . . . . . . . . . .
Inhaltszusammenfassung zur Seite Nr. 14
R Table 9-21: PHY Identifier (Registers 2 and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Table 9-22: SGMII Auto-Negotiation Advertisement (Register 4) . . . . . . . . . . . . . . . . . . 139 Table 9-23: SGMII Auto-Negotiation Link Partner Ability Base (Register 5) . . . . . . . . 140 Table 9-24: SGMII Auto-Negotiation Expansion (Register 6) . . . . . . . . . . . . . . . . . . . . . . 141 Table 9-25: SGMII Auto-Negotiation Next Page Transmit (Register 7). .
Inhaltszusammenfassung zur Seite Nr. 15
R Preface About This Guide The LogiCORE™ IP Ethernet 1000BASE-X PCS/PMA or SGMII User Guide provides information about generating a Xilinx Ethernet 1000BASE-X PCS/PMA or SGMII core, customizing and simulating the core using the provided example design, and running the design files through implementation using the Xilinx tools. Guide Contents This guide contains the following information. • Preface, “About This Guide” introduces the organization and purpose of this guide and defines the conve
Inhaltszusammenfassung zur Seite Nr. 16
R Preface: About This Guide • Chapter 11, “Dynamic Switching of 1000BASE-X and SGMII Standards” provides general guidelines for using the core to perform dynamic standards switching between 1000BASE-X and SGMII. • Chapter 12, “Constraining the Core” defines the constraint requirements of the core. • Chapter 13, “Interfacing to Other Cores” describes additional design considerations associated with implementing the core with the 1-Gigabit Ethernet MAC and Tri- Mode Ethernet MAC cores. • Chap
Inhaltszusammenfassung zur Seite Nr. 17
R Conventions Convention Meaning or Use Example An optional entry or parameter. However, in bus ngdbuild [option_name] Square brackets [ ] specifications, such as design_name bus[7:0], they are required. A list of items from which you Braces { } lowpwr ={on|off} must choose one or more Separates items in a list of Vertical bar | lowpwr ={on|off} choices IOB #1: Name = QOUT’ Vertical ellipsis IOB #2: Name = CLKIN’ . Repetitive material that has . . been omitted . . . Repetitive m
Inhaltszusammenfassung zur Seite Nr. 18
R Preface: About This Guide 20 www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008
Inhaltszusammenfassung zur Seite Nr. 19
R Chapter 1 Introduction The Ethernet 1000BASE-X PCS/PMA or SGMII core is a fully verified solution that supports Verilog HDL and VHDL. In addition, the example design provided with the core supports both Verilog and VHDL. This chapter introduces the Ethernet 1000BASE-X PCS/PMA or SGMII core and provides related information, including recommended design experience, additional resources, technical support, and methods for submitting feedback to Xilinx. About the Core The Ethernet 1000BASE-X
Inhaltszusammenfassung zur Seite Nr. 20
R Chapter 1: Introduction Additional Core Resources For detailed information and updates about the Ethernet 1000BASE-X PCS/PMA or SGMII core, see the following documents, located on the Xilinx Ethernet 100BASE-X PCS/PMA product page. • Ethernet 1000BASE-X PCS/PMA or SGMII Data Sheet • Ethernet 1000BASE-X PCS/PMA or SGMII Getting Started Guide After generating the core, the following documents are available in the document directory: • Ethernet 1000BASE-X PCS/PMA or SGMII Release Notes • Ether
