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TMS320C645x DSP
Ethernet Media Access Controller (EMAC)/
Management Data Input/Output (MDIO)
User's Guide
Literature Number: SPRU975B
August 2006
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2 SPRU975B–August 2006 Submit Documentation Feedback
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Contents Preface.............................................................................................................................. 10 1 Introduction.............................................................................................................. 11 1.1 Purpose of the Peripheral ..................................................................................... 11 1.2 Features ..............................................................................................
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4.15 MDIO User PHY Select Register 1 (USERPHYSEL1) .................................................... 80 5 EMAC Port Registers ................................................................................................. 81 5.1 Introduction...................................................................................................... 81 5.2 Transmit Identification and Version Register (TXIDVER) ................................................. 85 5.3 Transmit Control Register (TXCON
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5.48 Transmit Channel 0-7 Completion Pointer Register (TXnCP)........................................... 134 5.49 Receive Channel 0-7 Completion Pointer Register (RXnCP)........................................... 135 5.50 Network Statistics Registers................................................................................. 136 Appendix A Glossary ...................................................................................................... 145 Appendix B Revision History .........
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List of Figures 1 EMAC and MDIO Block Diagram ........................................................................................ 12 2 Ethernet Configuration with MII Interface ............................................................................... 16 3 Ethernet Configuration with RMII Interface ............................................................................. 18 4 Ethernet Configuration with GMII Interface ................................................................
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53 Receive Buffer Offset Register (RXBUFFEROFFSET).............................................................. 109 54 Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH).............................. 110 55 Receive Channel n Flow Control Threshold Register (RXnFLOWTHRESH)..................................... 111 56 Receive Channel n Free Buffer Count Register (RXnFREEBUFFER) ............................................ 112 57 MAC Control Register (MACCONTROL) .............
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List of Tables 1 Interface Selection Pins ................................................................................................... 16 2 EMAC and MDIO Signals for MII Interface ............................................................................. 17 3 EMAC and MDIO Signals for RMII Interface ........................................................................... 19 4 EMAC and MDIO Signals for GMII Interface ...................................................................
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50 Receive Unicast Enable Set Register (RXUNICASTSET) Field Descriptions .................................... 106 51 Receive Unicast Clear Register (RXUNICASTCLEAR) Field Descriptions ....................................... 107 52 Receive Maximum Length Register (RXMAXLEN) Field Descriptions ............................................ 108 53 Receive Buffer Offset Register (RXBUFFEROFFSET) Field Descriptions........................................ 109 54 Receive Filter Low Priority Frame Thresho
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Preface SPRU975B–August 2006 Read This First About This Manual This document provides a functional description of the Ethernet Media Access Controller (EMAC) and Physical layer (PHY) device Management Data Input/Output (MDIO) module integrated with TMS320C645x devices. Notational Conventions This document uses the following conventions. • Hexadecimal numbers are shown with the suffix h. For example, the following number is 40 hexadecimal (decimal 64): 40h. • Registers in this document are shown
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User's Guide SPRU975B–August 2006 Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) 1 Introduction This document provides a functional description of the Ethernet Media Access Controller (EMAC) and Physical layer (PHY) device Management Data Input/Output (MDIO) module integrated with TMS320C645x (C645x) devices. Included are the features of the EMAC and MDIO modules, a discussion of their architecture and operation, how these modules connect to the outside world, and th
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www.ti.com Introduction 1.3 Functional Block Diagram Figure 1 shows the three main functional modules of the EMAC/MDIO peripheral: • EMAC control module • EMAC module • MDIO module The EMAC control module is the main interface between the device core processor and the EMAC module and MDIO module. The EMAC control module contains the necessary components to allow the EMAC to make efficient use of device memory, plus it controls device interrupts. The EMAC control module incorporates 8K byte inter
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www.ti.com Introduction 1.4 Industry Standard(s) Compliance Statement The EMAC peripheral conforms to the IEEE 802.3 standard, describing the “Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and Physical Layer” specifications. ISO / IEC has also adopted the IEEE 802.3 standard and re-designated it as ISO/IEC 8802-3:2000(E). In difference from this standard, the EMAC peripheral integrated with the C645x devices does not use the transmit coding error signal MTXER. In
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www.ti.com EMAC Functional Architecture 2 EMAC Functional Architecture This chapter discusses the architecture and basic function of the EMAC peripheral. 2.1 Clock Control The frequencies for the transmit and receive clocks are fixed by the IEEE 802.3 specification as shown below: • 2.5 Mhz at 10 Mbps • 25 Mhz at 100 Mbps • 125 MHz at 1000 Mbps The C645x device uses two PLL controllers to generate all of the clocks that the DSP needs. The primary PLL controller generates a peripheral clock (SYSC
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www.ti.com EMAC Functional Architecture For timing purposes, data in 10/100 mode is transmitted and received with reference to MTCLK and MRCLK, respectively. For 1000 Mbps mode, receive timing is the same, but transmit is relative to GMTCLK. 2.1.4 RGMII Clocking When the RGMII interface is selected by setting MACSEL to 11b, you must configure the internal clock (SYSCLK1) to a 125 MHz frequency by setting the divider for the secondary PLL controller to /5. This provides a reference clock that you
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www.ti.com EMAC Functional Architecture 2.3 System Level Connections The C645x device supports four different interfaces to a physical layer device. You can only transfer data on one interface at a given time. Each of these interfaces is selected in hardware via the configuration pins (MACSEL[1:0]). Table 1 shows the possible settings for these configuration pins. Table 1. Interface Selection Pins MACSEL [1:0] Interface 00 MII 01 RMII 10 GMII 11 RGMII 2.3.1 Media Independent Interface (MII) Conn
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www.ti.com EMAC Functional Architecture Table 2 summarizes the individual EMAC and MDIO signals for the MII interface. For more information, refer to either the IEEE 802.3 standard or ISO/IEC 8802-3:2000(E). The EMAC module does not include a transmit error (MTXER) pin. If a transmit error occurs, CRC inversion is used to negate the validity of the transmitted frame. Table 2. EMAC and MDIO Signals for MII Interface Signal Name I/O Description MTCLK I Transmit clock (MTCLK). The transmit clock is
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www.ti.com EMAC Functional Architecture 2.3.2 Reduced Media Independent Interface (RMII) Connections Figure 3 shows a device with integrated EMAC and MDIO interfaced via a RMII connection. This interface is only available in 10 Mbps and 100 Mbps modes. The RMII interface is only supported in full-duplex mode for the C645x family of devices. Figure 3. Ethernet Configuration with RMII Interface MTXD[1−0] MTXEN MCRSDV Transformer Physical System layer MREFCLK core device MRXD[1−0] RJ−45 (PHY) MRXER
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www.ti.com EMAC Functional Architecture The RMII interface has the same functionality as the MII, but it does so with a reduced number of pins, thus lowering the total cost for an application. In devices incorporating many PHY interfaces such as switches, the number of pins can add significant cost as the port counts increase. Table 3 summarizes the individual EMAC and MDIO signals for the RMII interface. The RMII interface does not include an MCOL signal. A collision is detected from the receiv
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www.ti.com EMAC Functional Architecture 2.3.3 Gigabit Media Independent Interface (GMII) Connections Figure 4 shows a device with integrated EMAC and MDIO interfaced via a GMII connection. This interface is available in 10 Mbps, 100 Mbps, and 1000 Mbps modes. Figure 4. Ethernet Configuration with GMII Interface MTCLK GMTCLK 2.5 MHz, MTXD[7−0] 25 MHz, MTXEN or 125 MHz MCOL MCRS Physical System layer MRCLK Transformer core device MRXD[7−0] (PHY) MRXDV MRXER RJ−45 MDCLK MDIO The GMII interface supp
