Inhaltszusammenfassung zur Seite Nr. 1
User’s Manual
µ PD754144, 754244
4-Bit Single-Chip Microcontrollers
µ PD754144
µ PD754244
Document No. U10676EJ3V0UM00 (3rd edition)
Date Published November 2002 N CP(K)
1997
Printed in Japan
Inhaltszusammenfassung zur Seite Nr. 2
[MEMO] 2 User’s Manual U10676EJ3V0UM
Inhaltszusammenfassung zur Seite Nr. 3
NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build stati
Inhaltszusammenfassung zur Seite Nr. 4
These commodities, technology or software, must be exported in accordance with the export administration regulations of the exporting country. Diversion contrary to the law of that country is prohibited. • The information in this document is current as of July, 2002. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products.
Inhaltszusammenfassung zur Seite Nr. 5
Regional Information Some information contained in this document may vary from country to country. Before using any NEC Electronics product in your application, pIease contact the NEC Electronics office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • Ordering information • Product release schedule • Availability of related technical literature • Development environment specifications (for example, specifications
Inhaltszusammenfassung zur Seite Nr. 6
Major Revisions in This Edition Pages Description p.210 Correction of description in figure in 7.9 Application of Interrupt (6) Executing pending interrupt - interrupt occurs during interrupt service (INTBT has higher priority and INTT0 and INTT2 have lower priority) p.253 Correction of instruction code of “BR BCDE” in 11.3 Opcode of Each Instruction p.296 Deletion of flash-related products in configuration diagram in APPENDIX A DEVELOPMENT TOOLS p.297 in 2nd edition Deletion of APPENDIX A LI
Inhaltszusammenfassung zur Seite Nr. 7
INTRODUCTION Readers This manual is intended for user engineers who wish to understand the functions of the µ PD754144 and 754244 and design application systems using these microcontrollers. Purpose This manual is intended to give users an understanding of the hardware functions of the µ PD754144 and 754244 described in the Organization below. Organization This manual contains the following information. • General • Pin Functions • Features of Architecture and Memory Map • Internal CPU Functions
Inhaltszusammenfassung zur Seite Nr. 8
Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents related to devices Document Name Document No. µ PD754144, 754244 Data Sheet U10040E µ PD754144, 754244 User’s Manual This manual 75XL Series Selection Guide U10453E Documents related to development tools (software) (user’s manuals) Document Name Document No. RA75X Assembler Package Operation U12622E Language U12385E Structured Ass
Inhaltszusammenfassung zur Seite Nr. 9
TABLE OF CONTENTS CHAPTER 1 GENERAL ..................................................................................................................... 17 1.1 Functional Outline ............................................................................................................. 18 1.2 Ordering Information ......................................................................................................... 19 1.3 Differences Between Series Products ................................
Inhaltszusammenfassung zur Seite Nr. 10
4.6 Accumulator........................................................................................................................ 70 4.7 Stack Pointer (SP) and Stack Bank Select Register (SBS) .......................................... 70 4.8 Program Status Word (PSW)............................................................................................. 74 4.9 Bank Select Register (BS) ................................................................................................ 78
Inhaltszusammenfassung zur Seite Nr. 11
CHAPTER 7 INTERRUPT AND TEST FUNCTIONS ........................................................................ 186 7.1 Configuration of Interrupt Controller .............................................................................. 186 7.2 Types of Interrupt Sources and Vector Table ................................................................. 188 7.3 Hardware Controlling Interrupt Function ....................................................................... 190 7.4 Interrupt Sequen
Inhaltszusammenfassung zur Seite Nr. 12
11.4.10 Branch instructions ................................................................................................................ 279 11.4.11 Subroutine/stack control instructions .................................................................................... 283 11.4.12 Interrupt control instructions.................................................................................................. 287 11.4.13 Input/output instructions .............................................
Inhaltszusammenfassung zur Seite Nr. 13
LIST OF FIGURES (1/3) Figure No. Title Page 3-1 Selecting MBE = 0 Mode and MBE = 1 Mode .................................................................................. 33 3-2 Data Memory Configuration and Addressing Range for Each Addressing Mode............................ 35 3-3 Updating Address of Static RAM ....................................................................................................... 39 3-4 Example of Using Register Banks .........................................
Inhaltszusammenfassung zur Seite Nr. 14
LIST OF FIGURES (2/3) Figure No. Title Page 6-18 Example of Incorrect Resonator Connection ..................................................................................... 109 6-19 CPU Clock Switching Example .......................................................................................................... 113 6-20 Block Diagram of Basic Interval Timer/Watchdog Timer ................................................................... 114 6-21 Format of Basic Interval Timer Mode Regi
Inhaltszusammenfassung zur Seite Nr. 15
LIST OF FIGURES (3/3) Figure No. Title Page 7-9 Interrupt Nesting by Changing Interrupt Status Flag ........................................................................ 199 7-10 Block Diagram of KR4 to KR7 ............................................................................................................ 213 7-11 Format of INT2 Edge Detection Mode Register (IM2) ...................................................................... 214 8-1 Releasing Standby Mode.....................
Inhaltszusammenfassung zur Seite Nr. 16
LIST OF TABLES Table No. Title Page 2-1 Pin Functions of Digital I/O Ports ....................................................................................................... 24 2-2 Functions of Non-Port Pins ................................................................................................................ 25 2-3 Recommended Connection of Unused Pins ...................................................................................... 31 3-1 Addressing Modes ..................
Inhaltszusammenfassung zur Seite Nr. 17
CHAPTER 1 GENERAL The µ PD754144 and 754244 are 4-bit single-chip microcontrollers in the NEC 75XL Series, the successor to the 75X Series that boasts a wealth of variations. The µ PD754144 and 754244 have extended CPU functions compared to the µ PD75048, a 75X Series product with on-chip EEPROM, enabling high-speed and low voltage (1.8 V) operation. This model is available in a small plastic SSOP (7.62 mm (300)). The features of the µ PD754144 are as follows: • Low-voltage operation: VDD = 1.8
Inhaltszusammenfassung zur Seite Nr. 18
CHAPTER 1 GENERAL 1.1 Functional Outline Item µ PD754144 µ PD754244 Instruction execution time • 4, 8, 16, 64 µ s (at fCC = 1.0 MHz) • 0.95, 1.91, 3.81, 15.3 µ s (at fX = 4.19 MHz) • 0.67, 1.33, 2.67, 10.7 µ s (at fX = 6.00 MHz) On-chip Mask ROM 4096 × 8 bits (0000H to 0FFFH) memory RAM 128 × 4 bits (000H to 07FH) EEPROM 16 × 8 bits (400H to 41FH) System clock oscillator RC oscillator Crystal/ceramic oscillator (External resistor and capacitor) General-purpose registers • 4-bit operation: 8
Inhaltszusammenfassung zur Seite Nr. 19
CHAPTER 1 GENERAL 1.2 Ordering Information Part Number Package µ PD754141GS-×××-BA5 20-pin plastic SOP (7.62 mm (300)) µ PD754141GS-×××-GJG 20-pin plastic SSOP (7.62 mm (300)) µ PD754244GS-×××-BA5 20-pin plastic SOP (7.62 mm (300)) µ PD754244GS-×××-GJG 20-pin plastic SSOP (7.62 mm (300)) Remark ××× indicates ROM code suffix. 1.3 Differences Between Series Products Item µ PD754144 µ PD754244 Instruction execution time 4, 8, 16, 64 µ s (at fCC = 1.0 MHz) • 0.95, 1.91, 3.81, 15.3 µ s (at fX = 4
Inhaltszusammenfassung zur Seite Nr. 20
CHAPTER 1 GENERAL 1.4 Block Diagram Port 3 4 P30 to P33 Basic interval timer/watchdog timer SP (8) INTBT RESET CY ALU Port 6 4 P60 to P63 PTO0/P30 8-bit timer counter #0 INTT0 TOUT SBS Program counter INTT1 Bank Port 7 4 P70 to P73 8-bit timer PTO1/P31 counter #1 General reg. Cascaded 16-bit timer Program memory Port 8 P80 Data memory counter 8-bit timer (ROM) (RAM) PTO2/P32 4096 × 8 bits counter #2 128 × 4 bits INTT2 EEPROM 16 × 8 bits INT0/P61 Bit seq. buffer (16) Decode and control KRREN
