Inhaltszusammenfassung zur Seite Nr. 1
®
Intel 5100 Memory Controller Hub
Chipset for Communications,
Embedded, and Storage Applications
Thermal/Mechanical Design Guide
July 2008
Revision 003US
Order Number: 318676-003US
Inhaltszusammenfassung zur Seite Nr. 2
Legal Lines and Disclaimers INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS
Inhaltszusammenfassung zur Seite Nr. 3
® Intel 5100 MCH Chipset Contents 1.0 Introduction ..............................................................................................................6 1.1 Design Flow........................................................................................................6 1.2 Definition of Terms..............................................................................................7 1.3 Related Documents ...........................................................................
Inhaltszusammenfassung zur Seite Nr. 4
® Intel 5100 MCH Chipset Figures 1 Thermal Design Process ............................................................................................. 7 2 MCH Package Dimensions (Top View)..........................................................................10 3 MCH Package Dimensions (Side View) .........................................................................10 4 MCH Package Dimensions (Bottom View).....................................................................11 5 Processor
Inhaltszusammenfassung zur Seite Nr. 5
® Intel 5100 MCH Chipset Revision History Date Revision Description Added the CompactPCI* reference solution July 2008 003 Added Figure 26, Figure 27, and Figure 28 Updated the supplier information February 2008 002 Updated the TDP value to 25.7 W in Table 3 Max config November 2007 001 Initial release Revision Number Descriptions Revision Associated Life Cycle Milestone Release Information 0.0 POP L3 Closure Initial Documentation - Typically Internal Only 0.1–0.4 When Needed Project Dependent -
Inhaltszusammenfassung zur Seite Nr. 6
® Intel 5100 MCH Chipset 1.0 Introduction As the complexity of computer systems increases, so do the power dissipation requirements. Care must be taken to ensure that the additional power is properly dissipated. Typical methods to improve heat dissipation include selective use of ducting, and/or passive heatsinks. The goals of this document are to: • Outline the thermal and mechanical operating limits and specifications for the ® ® Intel 5100 Memory Controller Hub Chipset (Intel 5100 MCH Chi
Inhaltszusammenfassung zur Seite Nr. 7
® Intel 5100 MCH Chipset Figure 1. Thermal Design Process Step 1: Thermal Simulation • Package Level Thermal Models Step 2: Heatsink Design • Thermal Model User’s Guide and Selection • Reference Heatsinks • Reference Mounting Hardware Step 3: Thermal Validation • Vendor Contacts • Thermal Testing Software • Thermal Test Vehicle • User Guides 1.2 Definition of Terms Table 1. Definition of Terms Term Definition Flip Chip Ball Grid Array. A package type defined by a plastic substrate wh
Inhaltszusammenfassung zur Seite Nr. 8
® Intel 5100 MCH Chipset 1.3 Related Documents ® Intel Electronic Design Kits (EDKs) provide online, real-time collateral updates. The ® following links take you to the EDK server and require you to log into Intel Business Link (IBL). • Quad-Core and Dual-Core Intel® Xeon® Processor 5000 Sequence with Intel® 5100 Memory Controller Hub Chipset for Communications, Embedded, and Storage Applications • Intel® Core™2 Duo Processors T9400 and SL9400 and Intel® 5100 Memory Controller Hub Chipset
Inhaltszusammenfassung zur Seite Nr. 9
® Intel 5100 MCH Chipset Table 2. Related Documents (Sheet 2 of 2) Document Document Number/URL ® Intel I/O Controller Hub 9 (ICH9) Family Thermal and http://www.intel.com/ (316974) Mechanical Design Guidelines ® ® Quad-Core and Dual-Core Intel Xeon Processor 5000 ® Sequence with Intel 5100 Memory Controller Hub Chipset for Note 1 Communications, Embedded, and Storage Applications – Platform Design Guide ® ® Quad-Core Intel Xeon Processor 5300 Series Datasheet http://www.intel.com/ (315569)
Inhaltszusammenfassung zur Seite Nr. 10
® Intel 5100 MCH Chipset Figure 2. MCH Package Dimensions (Top View) Handling Exclusion Area 38.5 mm, MCH 38.5 mm. 42.5 mm. IHS 42.5 mm. Figure 3. MCH Package Dimensions (Side View) 4.23 ± 0.146 mm 3.79 ± 0.144 mm IHS Substrate 2.44 ± 0.071 mm 0.20 See note 4. 0.20 –C– Seating Plane 0.435 ± 0.025 mm See note 1. See note 3 Notes: 1. Primary datum -C- and seating plan are defined by the spherical crowns of the solder balls (shown before motherboard attach) 2. All dimensions and tolerances conform
Inhaltszusammenfassung zur Seite Nr. 11
® Intel 5100 MCH Chipset Figure 4. MCH Package Dimensions (Bottom View) AV AU AT AR AP AN AM AL AK AJ AH AG AF AE AD AC AB AA 42.5 + 0.05 Y - A - W V U T R P N M L 20.202 K J H G F E D 37X 1.092 C B A 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 12 3 5 7 9 11 13 15 17 19 21 23 25729 31 33 3537 A 37X 1.092 20.202 42.5 + 0.05 B 0.2 C A Notes: 1. All dimensions are in millimeters. 2. All dimensions and tolerances conform to ANSI Y14.5M-1994. 2.1 Package Mechanical Requirements ® The Intel 5
Inhaltszusammenfassung zur Seite Nr. 12
® Intel 5100 MCH Chipset Note: These specifications apply to uniform compressive loading in a direction perpendicular to the IHS top surface. Note: These specifications are based on limited testing for design characterization. Loading limits are for the package only. 3.0 Thermal Specifications 3.1 Thermal Design Power (TDP) Analysis indicates that real applications are unlikely to cause the MCH component to consume maximum power dissipation for sustained time periods. Therefore, in order to
Inhaltszusammenfassung zur Seite Nr. 13
® Intel 5100 MCH Chipset The case-to-local ambient thermal characterization parameter (Ψ ) is used as a CA measure of the thermal performance of the overall thermal solution. It is defined by Equation 1 and is measured in units of °C/W. Equation 1. Case-to-local Ambient Thermal Characterization Parameter (Ψ ) CA T – T CASE LA -- -- -- -- -- -- -- -- - - - - - - - -- Ψ = CA TDP The case-to-local ambient thermal characterization parameter, Ψ , is comprised of CA Ψ , the thermal interface materi
Inhaltszusammenfassung zur Seite Nr. 14
® Intel 5100 MCH Chipset 2. Define a target local ambient temperature, T . LA 3. Use Equation 1 and Equation 2 to determine the required thermal performance needed to cool the device. The following provides an example of how you might determine the appropriate performance targets. Assume: •TDP = 25.0 W and T = 105 °C CASE • Local processor ambient temperature, T , = 60 °C LA Then the following could be calculated using Equation 1 for the given chipset configuration. T – T 105 – 60 CASE LA --
Inhaltszusammenfassung zur Seite Nr. 15
® Intel 5100 MCH Chipset ® Table 4 summarizes the thermal budget required to adequately cool the Intel 5100 MCH Chipset in one configuration using a TDP of 25 W. Further calculations would need to be performed for different TDPs. Because the results are based on air data at sea level, a correction factor would be required to estimate the thermal performance at other altitudes. Table 4. Required Heatsink Thermal Performance (Ψ ) CA Device Ψ (°C/W) at T = 45 °C Ψ (°C/W) at T = 60 °C CA LA CA L
Inhaltszusammenfassung zur Seite Nr. 16
® Intel 5100 MCH Chipset Table 5. Thermocouple Attach Support Equipment Item Description Part Number Measurement and Output Microscope Olympus* light microscope or equivalent SZ-40 Digital multi-meter Digital multi-meter for resistance measurement Not Available Test Fixture(s) Micromanipulator set from YOU Ltd. or equivalent mechanical 3D arm with needle 1 Micromanipulator YOU-3 (not included) to maintain T bead location during the attach process C Miscellaneous Hardware Locite* 498* Super Bon
Inhaltszusammenfassung zur Seite Nr. 17
® Intel 5100 MCH Chipset Figure 6. IHS Groove Dimensions ® Intel 5100 Memory Controller Hub Chipset for Communications, Embedded, and Storage Applications July 2008 TDG Order Number: 318676-003US 17
Inhaltszusammenfassung zur Seite Nr. 18
® Intel 5100 MCH Chipset Figure 7. Orientation of Thermocouple Groove Relative to Package Pin 5.1.4 Thermocouple Conditioning and Preparation 1. Use a calibrated thermocouple as specified in Table 5. 2. Measure the thermocouple resistance by holding both wires on one probe and the tip of the thermocouple to the other probe of the DMM (compare to thermocouple resistance specifications). 3. Straighten the wire for about 38 mm (1½") from the bead to place it inside the channel. 4. Bend the tip
Inhaltszusammenfassung zur Seite Nr. 19
® Intel 5100 MCH Chipset 2. Place the thermocouple wire inside the groove letting the exposed wire and bead extend about 3.2 mm (0.125") past the end of the groove. Secure it with Kapton tape (Figure 9). 3. Lift the wire at the middle of groove with tweezers and bend the front of the wire to place the thermocouple in the channel ensuring that the tip is in contact with the end of the channel grooved in the IHS (Figure 10 A and B). 4. Place the MCH under the microscope unit (similar to the on
Inhaltszusammenfassung zur Seite Nr. 20
® Intel 5100 MCH Chipset Figure 10. Thermocouple Bead Placement Figure 11. Positioning Bead on Groove ® Intel 5100 Memory Controller Hub Chipset for Communications, Embedded, and Storage Applications TDG July 2008 20 Order Number: 318676-003US
